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buzzword [2018/11/01 13:29] mpatelbuzzword [2019/09/20 11:09] (current) juang
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   * Error Correcting Codes (ECC)   * Error Correcting Codes (ECC)
  
-===== Lecture 2 (20.09 Wed.) =====+===== Lecture 2 (20.09 Thu.) =====
   * Rowhammer   * Rowhammer
   * Memory reliability   * Memory reliability
Line 577: Line 577:
  
 ===== Lecture 14b (1.11 Thu.) ===== ===== Lecture 14b (1.11 Thu.) =====
 +  * 3D NAND Flash Memory
 +  * BCH ECC
 +  * Bit Error Rate
 +  * Capacitative Coupling
 +  * Charge Trap Based 3D Flash Cell
 +  * Control Gate
 +  * Data Retention in Flash Memory
 +  * Early Retention Loss
 +  * ECC Correction Capability
 +  * Error Correction Code
 +  * Fast-/slow-leaking Flash Memory Cells
 +  * Flash Correct-and-Refresh (FCR)
 +  * Flash Memory
 +  * Flash Memory Block
 +  * Flash Memory Cell Threshold Voltage 
 +  * Flash Memory Endurance
 +  * Flash Memory Page
 +  * Flash Memory String
 +  * Flash Read Disturb Errors
 +  * Floating Gate Transistor
 +  * Incremental Step Pulse Programming (ISPP0)
 +  * LI-RAID: Layer-Interleaved RAID
 +  * NAND Flash
 +  * NOR Flash
 +  * P/E Cycle
 +  * P/E cycle count (PEC)
 +  * Planar vs. 3D NAND Flash Memory
 +  * Process Variation
 +  * Raw Bit Error Rate (RBER)
 +  * Read Reference Voltage
 +  * Read Reference Voltage Prediction
 +  * Read-Disturbance Error
 +  * Read-Retry
 +  * Sense Amplifiers
 +  * Solid-State Drive
 +  * Threshold Voltage Distribution
 +  * Uncorrectable Bit Error Rate (UBER)
 +  * Uncorrectable Errors
 +  * Wearout Period
  
 +===== Lecture 15 (14.11 Wed.) =====
 +  * Program Interference
 +  * Voltage threshold shift learning
 +  * Read reference voltage prediction
 +  * Victim/Aggressor word line
 +  * Conditional Reading
 +  * Neighbor assisted correction
 +  * Read Disturb Errors in Flash memory
 +  * weak programming
 +  * pass-through voltage
 +  * Vpass Tuning
 +  * Unused ECC capabilities
 +  * Disturb-Prone cells
 +  * Disturb-resistant cells
 +  * Read Disturb Oriented Error Recovery (RDR)
 +  * Retention Error Handling
 +  * Retention Failure Recovery (RFR)
 +  * Retention Optimized Reading 
 +  * bathtub curve
 +  * Read Disturbance
 +  * Write Amplification
 +  * Retention interference
 +  * Retention loss
 +  * process variation
 +  * Raw Bit Error Rate (RBER)
 +  * Hot/Cold Page
 +  * Write-hotness aware management
 +
 +===== Lecture 16 (15.11 Thu.) =====
 +  * Resource sharing 
 +  * Contention for resources
 +  * Multiple hardware contexts
 +  * Performance isolation
 +  * Revolving door analogy
 +  * Quality of Service (QoS)
 +  * Shared resource management
 +  * Utilization/efficiency
 +  * Uncontrolled (free-for-all) sharing
 +  * Unfair sharing
 +  * Unpredictable performance (or lack of QoS)
 +  * Service Level Agreement (SLA)
 +  * Overprovision
 +  * Partitioning (dedicated space)
 +  * Memory performance hog
 +  * FR-FCFS
 +  * Denial of Service (DoS)
 +  * Distributed DoS
 +  * Packet-switched routers
 +  * Inter-thread interference
 +  * QoS-aware memory systems
 +  * Smart resources
 +  * QoS-aware memory controller
 +  * QoS-aware interconnect
 +  * QoS-aware caches
 +  * Dumb resources
 +  * Injection control
 +  * Data mapping
 +  * Prioritization / requests scheduling
 +  * Fair memory scheduling
 +  * Stall-time tracking / estimation
 +  * Bank parallelism interference
 +  * Parallelism-aware scheduler
 +  * Request batching
 +  * PAR-BS
 +  * Within-batch scheduling
 +  * ATLAS
 +  * Thread ranking
 +  * Shortest job first
 +  * Shortest stall-time first
 +  * Multiple memory controllers
 +  * Thread clusters
 +  * TCM
 +  * Niceness
 +  * Throughput biased
 +  * Fairness biased
 +  * Misses Per Kilo Instructions (MPKI)
 +  * Priority shuffle
 +  * Vulnerability to interference
 +  * Tunable knobs
 +  * Blacklisting
 +  * Performance vs fairness vs simplicity
 +
 +===== Lecture 17 (21.11 Wed.) =====
 +  * Memory System
 +  * Memory Controller
 +  * Heterogeneous Agents
 +  * DASH
 +  * Staged memory scheduling (SMS) 
 +  * First-ready first-come first-serve (FR-FCFS)
 +  * Memory Interference-Induced Slowdown Estimation (MISE)
 +  * Service Level Agreements (SLA)
 +  * Stall-time Fair Memory (STFM)
 +  * Quality of Service (QoS) 
 +  * Soft QoS
 +  * Multithreaded applications
 +  * Row-Buffer Locality 
 +  * Channel Partitioning
 +  * Page mapping
 +  * request buffer
 +
 +===== Lecture 18a (22.11 Thu.) =====
 +
 +   * Fundamental interference control techniques
 +   * Core/Source throttling
 +   * Smart resources
 +   * Dynamic unfairness estimation
 +   * Throttling cores' memory access rates
 +   * FST: Fairness via Source Throttling
 +   * Runtime unfairness evaluation
 +   * Dynamic request throttling
 +   * Request injection rate
 +   * Application/Thread scheduling
 +   * Many-core on-chip communication
 +   * Shared cache bank
 +   * Spatial task scheduling
 +   * Clustering, balancing, isolation, and radial mapping
 +   * Network power
 +   * Microarchitecture unawareness
 +   * Operating-system-level metrics and microarchitecture-level metrics
 +   * Architecture-aware distributed resource management (DRM)
 +   * Interference-aware thread scheduling
 +   * Memory quality of service (QoS) approaches and techniques
 +   * Smart vs dump components
 +   * Cache interference management
 +   * Interconnect interference management
 +   * DRAM designs to reduce interference
 +   * SoftMC
 +   * PIM accelerators
 +   * Decoupled direct memory access (DDMA)
 +
 +===== Lecture 18b (22.11 Thu.) =====
 +
 +   * Multi-core issues in caching
 +   * Cache coherence
 +   * Flush-local and flush-global
 +   * Snoopy cache coherence
 +   * Free for all sharing
 +   * Controlled cache sharing
 +   * Hardware -based cache partitioning
 +   * Marginal utility of a cache way
 +   * Dynamic set sampling
 +   * UCP
 +   * Optimal partitioning: Greedy and look-ahead algorithms
 +   * Dynamic fair caching
 +   * Software-based shared cache partitioning
 +   * Page coloring
 +   * Static cache partitioning
 +   * Dynamic cache partitioning via page re-coloring
 +
 +===== Lecture 19a (28.11 Thu.) =====
 +   * Controlled Shared Caching
 +   * Cache spilling
 +   * Cooperative caching
 +   * DSR: Dynamic spill-receive
 +   * Set dueling
 +   * Cooperative caching
 +   * Handling shared data in provate caches
 +   * Non-uniform cache access
 +   * Multi-core cache efficiency
 +   * Cache compression
 +   * Decompression latency
 +   * Compression ratio
 +   * Zero compression
 +   * Frequent value compression
 +   * Frequent pattern compression
 +   * Base-delta immediate compression
 +   * Toggle-aware compression for GPU systems
 +   * Core-assisted bottleneck acceleration in GPUs
 +   * Cache placement
 +   * Cache insertion policies: MRU, LRU
 +   * LIP: LRU insertion position (Low-prioirity insertion policy)
 +   * BIP: Bimodal insertion policy
 +   * DIP: Dynamic insertion policy
 +   * Circular reference model
 +   * Cache pollution
 +   * Cache thrashing
 +   * Reuse prediciton
 +   * EAF: Evicted-address filter
 +   * TA-DIP: Thread-aware dynamic insertion policy
 +   * Run-time bypassing
 +   * Single-usage block prediction
 +   * SHIP: Signature-based block prediction
 +   * Miss classification table
 +   * s-curve
 +   * ASM: Application slowdown model
 +   * Cache access rate
 +   * Memory access rate
 +   * Auxilary tag store
 +
 +===== Lecture 19b (28.11 Thu.) =====
 +   * Heterogeneity and asymmetry
 +   * CRAY-1 design
 +   * Scalar machine and vector pipeline machine
 +   * RAIDR
 +   * DRAM + Phase change memory
 +   * Reliable, costly DRAM + Unreliable, cheap DRAM
 +   * Heterogeneous retention time
 +   * Tilera
 +   * Packet switching and circuit switching
 +   * TDN, MDN, IDN, UDN, and STN
 +   * General purpose vs special purpose
 +   * Heterogeneity of CPU and GPUs
 +   * Predictability and robustness
 +
 +===== Lecture 20 (29.11 Thu.) =====
 +  * DRAM
 +  * NVM
 +  * Flash
 +  * Processing in Memory
 +  * Hardware Security
 +  * Heterogeneous Multi-Core Systems
 +  * Bottleneck Acceleration
 +  * Heterogeneity (Asymmetry)
 +  * Symmetric design 
 +  * One-size-fits-all
 +  * Quality of Service (QoS)
 +  * Hybrid Memory Controllers
 +  * Heterogeneous agents (e.g., CPUs, GPUs, and HWAs)
 +  * Heterogeneous memories: Fast vs. Slow DRAM
 +  * Heterogeneous interconnects: Control, Data, Synchronization
 +  * Amdahl’s Law
 +  * Synchronization overhead
 +  * Load imbalance overhead
 +  * Resource sharing overhead
 +  * Sequential portions (Amdahl’s “serial part”)
 +  * Critical sections
 +  * Barriers
 +  * Asymmetric Chip Multiprocessor (ACMP)
 +  * Bottleneck Acceleration
 +  * Staged Execution
 +  * Data Marshaling
 +  * Phase Change Memory
 +
 +===== Lecture 21 (05.12 Wed.) =====
 +  * GPU
 +  * Programming model
 +  * Sequential
 +  * SIMD
 +  * SPMD
 +  * SIMT
 +  * Warp (wavefront)
 +  * Multithreading of warps
 +  * Warp-level FGMT
 +  * Latency-hiding
 +  * Interleave warp execution
 +  * Registers of thread ID
 +  * Warp-based SIMD vs. Traditional SIMD
 +  * GPGPU programming
 +  * Inherent parallelism
 +  * Data parallelism
 +  * GPU main bottlenecks
 +  * CPU-GPU data transfers
 +  * DRAM memory
 +  * Task offloading
 +  * Serial code (host)
 +  * Parallel code (device)
 +  * Bulk synchronization
 +  * Transparent scalability
 +  * Memory hierarchy
 +  * Indexing and memory access
 +  * Streaming multiprocessor (SM)
 +  * Streaming processor (Vector lane)
 +  * Occupancy
 +  * Memory coalescing
 +  * Shared memory tiling
 +  * Bank conflict
 +  * Padding
 +  * SIMD utilization
 +  * Atomic operations
 +  * Histogram calculation
 +  * CUDA streams
 +  * Asynchronous transfers
 +  * Heterogeneous systems
 +  * Unified memory
 +  * System-wide atomic operations
 +  * Collaborative computing
 +  * CPU+GPU collaboration
 +  * Collaborative patterns
 +      * Data partitioning
 +      * Task partitioning
 +          * Coarse-grained
 +          * Fine-grained
 +  * Bézier surfaces
 +  * NVIDIA Pascal
 +  * NVIDIA Volta
 +  * Padding
 +  * Chai benchmark suite
 +
 +===== Lecture 22 (6.12 Thu.) =====
 +  * Persistent memory
 +  * Crash consistency
 +  * Checkpointing
 +  * Flynn´s taxonomy of computers
 +  * Parallelism
 +  * Performance
 +  * Power consumption
 +  * Cost efficiency
 +  * Dependability
 +  * Instruction level parallelism
 +  * Data parallelism
 +  * Task level parallelism
 +  * Multiprocessor
 +  * Loosely coupled
 +  * Tightly coupled
 +  * Shared global memory address space
 +  * Shared memory synchronization
 +  * Cache coherence
 +  * Memory consistency
 +  * Shared resource management
 +  * Interconnects
 +  * Programming issues in tightly coupled multiprocessor
 +  * Sublinear speedup
 +  * Linear speedup
 +  * Superlinear speedup
 +  * Unfair comparison
 +  * Cache/memory effect
 +  * Utilization
 +  * Redundancy
 +  * Efficiency
 +  * Amdahl's law
 +  * Bottlenecks in parallel portion
 +  * Ordering of operations
 +  * Sequential consistency
 +  * Weaker memory consistency
 +  * Memory fence instructions
 +  * Higher performance
 +  * Burden on the programmer
 +  * Coherence scheme
 +  * Valid/invalid
 +  * Write propagation
 +  * Write serialization
 +  * Update vs. Invalid
 +  * Cache coherence
 +  * Snoopy bus
 +  * Directory
 +  * Directory optimizations
 +  * Directory bypassing
 +  * Snoopy cache
 +  * Shared bus
 +  * VI protocol
 +  * MSI (Modified, Shared, Invalid)
 +  * Exclusive state
 +  * MESI (Modified, Exclusive, Shared, Invalid)
 +  * Illinois Protocol (MESI)
 +  * Broadcast
 +  * Bus request
 +  * Downgrade
 +  * Upgrade
 +  * Snoopy invalidation
 +  * Cache-to-cache transfer
 +  * Writeback
 +  * MOESI (Modified, Owned, Exclusive, Shared, Invalid)
 +  * Directory coherence
 +  * Race conditions
 +  * Totally-ordered interconnect
 +  * Directory-based protocols
 +  * Set inclusion test
 +  * Linked list
 +  * Bloom filters
 +  * Contention resolution
 +  * Ping-ponging
 +  * Synchronization
 +  * Shared-data-structure
 +  * Token Coherence
 +  * Virtual bus
 +
 +===== Lecture 23 (12.12 Wed.) =====
 +  * Interconnection Network, Interconnect
 +  * Topology
 +  * Routing
 +  * Buffering and Flow Control
 +  * Switch/Router
 +  * Channel
 +  * Wire
 +  * Packet
 +  * Path
 +  * Bus
 +  * Mesh, 2D Mesh
 +  * Throttling
 +  * Oversubscription
 +  * Network Interface
 +  * Link
 +  * Node
 +  * Message
 +  * Flit
 +  * Direct/Indirect Network
 +  * Radix
 +  * Regular/Irregular Topology
 +  * Routing Distance
 +  * Diameter
 +  * Bisection Bandwidth
 +  * Congestion
 +  * Blocking/non-blocking Interconnect
 +  * Crossbar
 +  * Ring
 +  * Tree
 +  * Omega
 +  * Hypercube
 +  * Torus
 +  * Butterfly
 +  * Arbitration
 +  * Point-to-Point
 +  * Multistage Network
 +  * Hop
 +  * Circuit Switching
 +  * Packet Switching
 +  * Tree saturation
 +  * Deadlock
 +  * Circular dependency
 +  * Oblivious Routing
 +  * Adaptive Routing
 +  * Packet Format
 +  * Header
 +  * Payload
 +  * Error Code
 +  * Virtual Channel Flow Control
 +
 +===== Lecture 24 (13.12 Thu.) =====
 +  * Load latency curve
 +  * Performance of interconnection networks
 +  * On-chip networks
 +  * Difference between off-chip and on-chip networks
 +  * Network buffers
 +  * Efficient routing
 +  * Advantages of on-chip interconnects
 +  * Pin constraints
 +  * Wiring resources
 +  * Disadvantages of on-chip interconnects
 +  * Energy/power constraint
 +  * Tradeoffs of interconnect design
 +  * Buffers in NoC routers
 +  * Bufferless routing
 +  * Flit-level routing
 +  * Deflection routing
 +  * Buffer and link energy consumption
 +  * Self-throttling
 +  * Livelock freedom problem
 +  * Golden packet for livelock freedom
 +  * Reassembly buffers
 +  * Packet retransmission
 +  * Packet scheduling
buzzword.txt · Last modified: 2019/09/20 11:09 by juang