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readings [2019/02/12 17:34]
127.0.0.1 external edit
readings [2019/12/12 10:02]
geraldod
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   * {{d7ce51c62671d5ffc1506786b0b7861ce00a.pdf| Jose A. Joao, M. Aater Suleman, Onur Mutlu, and Yale N. Patt, "​Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs". ISCA'​13}}   * {{d7ce51c62671d5ffc1506786b0b7861ce00a.pdf| Jose A. Joao, M. Aater Suleman, Onur Mutlu, and Yale N. Patt, "​Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs". ISCA'​13}}
   * {{22310236.pdf| Ed Grochowski, Ronny Ronen, John Shen, and Hong Wang, "Best of Both Latency and Throughput"​. ICCD 2004}}   * {{22310236.pdf| Ed Grochowski, Ronny Ronen, John Shen, and Hong Wang, "Best of Both Latency and Throughput"​. ICCD 2004}}
-  * {{amdahl.pdf|G. M. Amdahl, "​Validity of the single processor approach to achieving large scale computing capabilities,"​ AFIPS 1967}}+  * {{lecture1-amdahl.pdf|G. M. Amdahl, "​Validity of the single processor approach to achieving large scale computing capabilities,"​ AFIPS 1967}}
   * {{05389044.pdf|J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy, "​POWER4 System Microarchitecture"​. IBM J R&D 2002}}   * {{05389044.pdf|J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy, "​POWER4 System Microarchitecture"​. IBM J R&D 2002}}
   * {{719990eaab63a6bfa2988b5fd57a03b13229.pdf| Ron Kalla, Balaram Sinharoy, and Joel M. Tendler, "IBM Power5 Chip: A Dual-Core Multithreaded Processor"​. IEEE Micro 2004}}   * {{719990eaab63a6bfa2988b5fd57a03b13229.pdf| Ron Kalla, Balaram Sinharoy, and Joel M. Tendler, "IBM Power5 Chip: A Dual-Core Multithreaded Processor"​. IEEE Micro 2004}}
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 ===== Lecture 22 (6.12 Thu.) ===== ===== Lecture 22 (6.12 Thu.) =====
 === Required (lecture 22): === === Required (lecture 22): ===
-  * {{amdahl.pdf|G. M. Amdahl, "​Validity of the single processor approach to achieving large scale computing capabilities,"​ AFIPS 1967}}+  * {{lecture1-amdahl.pdf|G. M. Amdahl, "​Validity of the single processor approach to achieving large scale computing capabilities,"​ AFIPS 1967}}
   * {{lamport.pdf|L. Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs,"​ IEEE Transactions on Computers, 1979}}   * {{lamport.pdf|L. Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs,"​ IEEE Transactions on Computers, 1979}}
   * {{a_low-overhead_coherence_solution_for_multiprocessors_with_private_cache_memories.pdf|M. S. Papamarcos and J. H. Patel, "A low-overhead coherence solution for multiprocessors with private cache memories,"​ ISCA 1984}}   * {{a_low-overhead_coherence_solution_for_multiprocessors_with_private_cache_memories.pdf|M. S. Papamarcos and J. H. Patel, "A low-overhead coherence solution for multiprocessors with private cache memories,"​ ISCA 1984}}
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