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start [2018/09/11 10:57] – hhasan | start [2018/10/22 15:23] – [Contact] firtinac | ||
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The principles presented in the lecture are reinforced in the laboratory through the design and simulation of a register transfer (RT) implementation of a MIPS-like pipelined processor in System Verilog. In addition, we will develop a cycle-accurate simulator of this processor in C, and we will use this simulator to explore processor design options. | The principles presented in the lecture are reinforced in the laboratory through the design and simulation of a register transfer (RT) implementation of a MIPS-like pipelined processor in System Verilog. In addition, we will develop a cycle-accurate simulator of this processor in C, and we will use this simulator to explore processor design options. | ||
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^ ^ Name ^ E-mail ^ Office ^ Phone ^ Office Hours ^ | ^ ^ Name ^ E-mail ^ Office ^ Phone ^ Office Hours ^ | ||
| **Instructor** | [[https:// | | **Instructor** | [[https:// | ||
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- | | **Admin. Assistant** | [[https:// | + | | **Teaching Assistant** | Geraldo Francisco | < |
+ | | **Teaching Assistant** | [[https:// | ||
+ | | **Teaching Assistant** | [[https:// | ||
+ | | **Teaching Assistant** | [[https:// | ||
+ | | **Teaching | ||
+ | | **Teaching Assistant** | [[https:// |
start.txt · Last modified: 2019/02/12 16:34 by 127.0.0.1