tutorials
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**Combinational Logic, Hardware Description Lang. & Verilog** | **Combinational Logic, Hardware Description Lang. & Verilog** | ||
- | * 2018 Digital Circuits, Lecture 6 \\ Starts in lecture, slide 62: {{onur-DigitalDesign-2018-lecture6-combinational-logic-HDL-verilog-afterlecture.pdf|(PDF)}} | + | * 2018 Digital Circuits, Lecture 6 \\ Starts in lecture, slide 60: {{onur-DigitalDesign-2018-lecture6-combinational-logic-HDL-verilog-afterlecture.pdf|(PDF)}} |
- | * 2019 Digital Circuits, Lecture 7.2 \\ Starts in lecture, slide 10: {{onur-digitaldesign-2019-lecture7.2-hdl-afterlecture.pdf|(PDF)}} {{onur-digitaldesign-2019-lecture7.2-hdl-afterlecture.pptx| (PPT)}} \\ Starts in video 6:41: https:// | + | * 2019 Digital Circuits, Lecture 7.2 \\ Starts in lecture, slide 9: {{onur-digitaldesign-2019-lecture7.2-hdl-afterlecture.pdf|(PDF)}} {{onur-digitaldesign-2019-lecture7.2-hdl-afterlecture.pptx| (PPT)}} \\ Starts in video 6:41: https:// |
**Sequential Logic Design Using Verilog** | **Sequential Logic Design Using Verilog** | ||
- | * 2018 Digital Circuits, Lecture 7 \\ Tutorial starts (in lecture, slide 99): {{onur-DigitalDesign-2018-lecture7-sequential-logic-afterlecture.pdf|(PDF)}} | + | * 2018 Digital Circuits, Lecture 7 \\ Starts |
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- | * 2019 Digital Circuits, Lecture… | ||
==== Vivado Tutorials ==== | ==== Vivado Tutorials ==== | ||
Basic tutorial for implementing an adder on your FPGA [Taken from Digitaltechnik Spring 2018] \\ {{Digitaltechnik_lab2.pdf|Lab2 Manual}} | Basic tutorial for implementing an adder on your FPGA [Taken from Digitaltechnik Spring 2018] \\ {{Digitaltechnik_lab2.pdf|Lab2 Manual}} |
tutorials.1580120654.txt.gz · Last modified: 2020/01/27 10:24 by ewent