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buzzword [2020/11/27 19:29] kanellokbuzzword [2020/12/04 12:02] (current) – [Lecture 20 (03.12 Thu.)] Add Buzzwords for Lecture 21, 4/12 sjoao
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   * NVM-based PIM system   * NVM-based PIM system
  
 +
 +===== Lecture 16a (19.11 Thu.) =====
 +  * Emerging memory technology
 +  * Flash memory
 +  * Memory-centric system design
 +  * Phase change memoery
 +  * Charge memory
 +  * Resistive memory
 +  * Multi-level cell
 +  * Spin-Transfer Torque Magnetic RAM (STT-MRAM)
 +  * Memristors
 +  * Resistive RAM (RRAM or ReRAM)
 +  * Intel 3D Xpoint
 +  * Capacity-latency trade-off
 +  * Capacity-reliability trade-off
 +  * Endurance
 +  * Magnetic Tunnel Junction (MTJ)
 +  * Hybrid memory
 +  * Writing filtering
 +  * Data placement
 +  * Data access pattern
 +  * Row-buffer locality
 +  * Overall system performance impact
 +  * Memory-Level Parallelism (MLP)
 +  * Utility-based hybrid memory management
 +  * Hybrid Memory Systems 
 +  * Large (DRAM) Cache
 +  * TIMBER 
 +  * Two-Level Memory/Storage model
 +  * Volatile data 
 +  * Persistent data 
 +  * Single-level store
 +  * Unified Memory and storage
 +  * The Persistent Memory Manager (PMM)
 +  * ThyNVM 
 +
 +===== Lecture 16b (19.11 Thu.) =====
 +  * Heterogeneity 
 +  * Asymmetry in design
 +  * Amdahl's Law 
 +  * Synchronization overhead 
 +  * Load imbalance overhead
 +  * Resource sharing overhead
 +  * IBM Power4
 +  * IBM Power5
 +  * Niagara Processor
 +  * Performance vs. parallelism
 +  * Asymmetric Chip Multiprocessor (ACMP)
 +  * MorphCore
 ===== Lecture 17 (20.11 Fri.) ===== ===== Lecture 17 (20.11 Fri.) =====
   *Amdahl's Law   *Amdahl's Law
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   * Stages of Pipelined Programs   * Stages of Pipelined Programs
  
 +===== Lecture 20 (03.12 Thu.) =====
  
 +  * Memory ordering
 +  * Memory consistency
 +  * Parallel computer architecture
 +  * Multiprocessor operation
 +  * MIMD (multiple instruction, multiple data) machine
 +  * Performance-correctness trade-off
 +  * Cache coherence
 +  * Ordering of operations
 +  * Local ordering
 +  * Global ordering 
 +  * Memory fence instruction
 +  * Out-of-order execution 
 +  * Mutual exclusion
 +  * Protecting shared data
 +  * Critical section
 +  * Sequential consistency
 +  * Weaker memory consistency
 +  * Dataflow processor
  
 +
 +===== Lecture 21 (04.12 Fri.) =====
 +
 +  * Cache coherence
 +  * Memory consistency
 +  * Shared memory model
 +  * Software coherence
 +    * Coarse-grained (page-level)
 +    * Non-cacheable
 +    * Fine-grained (cache flush)
 +  * Hardware coherence
 +  * Valid/invalid
 +  * Write propagation
 +  * Write serialization
 +  * Update vs. Invalid
 +  * Snoopy bus
 +  * Directory
 +    * Exclusive bit
 +  * Directory optimizations (bypassing)
 +  * Snoopy cache
 +  * Shared bus
 +  * VI protocol
 +  * MSI (Modified, Shared, Invalid)
 +  * Exclusive state
 +  * MESI (Modified, Exclusive, Shared, Invalid)
 +  * Illinois Protocol (MESI)
 +  * Broadcast
 +  * Bus request
 +  * Downgrade/upgrade
 +  * Snoopy invalidation
 +  * Cache-to-cache transfer
 +  * Writeback
 +  * MOESI (Modified, Owned, Exclusive, Shared, Invalid)
 +  * Directory coherence
 +  * Race conditions
 +  * Totally-ordered interconnect
 +  * Directory-based protocols
 +  * Set inclusion test
 +  * Linked list
 +  * Bloom filters
 +  * Contention resolution
 +  * Ping-ponging
 +  * Synchronization
 +  * Shared-data-structure
 +  * Token Coherence
 +  * Coherence for NDAs
 +  * Optimistic execution
 +  * Signature
 +  * Commit/re-execute
buzzword.1606505396.txt.gz · Last modified: 2020/11/27 19:29 by kanellok