tutorials
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| tutorials [2020/01/27 10:33] – [Verilog Tutorials] ewent | tutorials [2020/09/15 07:12] (current) – [Verilog Tutorials] jispark | ||
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| **Combinational Logic, Hardware Description Lang. & Verilog** | **Combinational Logic, Hardware Description Lang. & Verilog** | ||
| - | * 2018 Digital Circuits, Lecture | + | * 2020 Digital Circuits, Lecture |
| - | * 2019 Digital Circuits, Lecture | + | * 2018 Digital Circuits, Lecture |
| **Sequential Logic Design Using Verilog** | **Sequential Logic Design Using Verilog** | ||
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| + | * 2020 Digital Circuits, Lecture 7b \\ Starts in lecture, slide 68: {{onur-digitaldesign-2020-lecture7b-hdl-beforelecture.pdf|(PDF)}} {{onur-digitaldesign-2020-lecture7b-hdl-beforelecture.pptx| (PPT)}} \\ Starts in video 40:30: https:// | ||
| * 2018 Digital Circuits, Lecture 7 \\ Starts in lecture, slide 99: {{onur-DigitalDesign-2018-lecture7-sequential-logic-afterlecture.pdf|(PDF)}} | * 2018 Digital Circuits, Lecture 7 \\ Starts in lecture, slide 99: {{onur-DigitalDesign-2018-lecture7-sequential-logic-afterlecture.pdf|(PDF)}} | ||
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| ==== Vivado Tutorials ==== | ==== Vivado Tutorials ==== | ||
| - | Basic tutorial for implementing an adder on your FPGA [Taken from Digitaltechnik Spring 2018] \\ {{Digitaltechnik_lab2.pdf|Lab2 Manual}} | + | Basic tutorial for implementing an adder on your FPGA [Taken from Digitaltechnik Spring 2018] \\ {{digitaltechnik_lab2.pdf|Lab2 Manual}} |
tutorials.1580121235.txt.gz · Last modified: 2020/09/10 08:05 (external edit)