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Buzzwords

Buzzwords are terms that are mentioned during the lecture which are particularly important to understand thoroughly. This page tracks the buzzwords for each of the lectures and can be used as a reference for finding gaps in your understanding of course material.

Lecture 1 (30.09 Thu.)

  • Computer Architecture
  • Levels of transformation
    • Algorithm
    • System software
    • Instruction Set Architecture (ISA)
    • Microarchitecture
    • Logic
  • Bioinformatics
  • Hardware security
  • Fault tolerance
  • Hardware-software cooperation
  • Heterogeneous processors
  • Hybrid main memory
  • Redundancy
  • Sustainability
  • RowHammer
  • Opportunities at the Bottom
  • Opportunities at the Top
  • Data movement bottleneck
  • Systems programming
  • Wafer-scale integration
  • Digital design
  • Abstraction layers
  • Expressive memory interfaces
  • Processing-in-DRAM
  • User-centric view
  • Productivity
  • Multi-core systems
  • Caches
  • DRAM memory controller
  • DRAM banks
  • Energy efficiency
  • Memory performance hog
  • Slowdown
  • Consolidation
  • QoS guarantees
  • Unfairness
  • Row decoder
  • Column address
  • DRAM cell
  • DRAM access transistor
  • DRAM refresh
  • DRAM retention time
  • Variable retention time
  • Retention time profile
  • Manufacturing process variation
  • Data pattern dependence
  • Variable retention time
  • Principled design
  • Design evaluation criteria
    • Functionality
    • Reliability
    • Space requirement
    • Cost
    • Expandability
  • Role of the (Computer) Architect
  • Bahnhof Stadelhofen
  • Santiago Calatrava
  • Oculus, NYC
  • Design constraints
  • Falling Water
  • Frank Lloyd Wright
  • Error Correcting Codes (ECC)
  • Hamming code
  • Hamming distance

Lecture 2 (01.10 Fri.)

  • RowHammer
  • Security
  • RowHammer in 2020
  • RowHammer solutions
  • Bioinformatics
  • High-throughput sequencing (HTS)
  • Nanopore Sequencing
  • Genome Sequence Analysis
  • Reference Genome
  • Read Mapping
  • Read Alignment/Verification
  • Edit Distance
  • In-Memory DNA Sequence Analysis
  • Memory Bottleneck
  • Role of the (Computer) Architect
  • Secure/Reliable/Safe Architectures
  • Bahnhof Stadelhofen
  • Santiago Calatrava
  • Oculus, NYC
  • Design constraints
  • Falling Water
  • Frank Lloyd Wright
  • Error Correcting Codes (ECC)
  • Hamming code
  • Hamming distance
  • TRRespass
  • Meltdown
  • Spectre
  • GRIM-Filter
  • Shouji
  • Hybrid Main Memory
  • Zoomorphic Architecture

Lecture 3a (07.10 Thu.)

  • Fundamentally Secure/Reliable/Safe Architectures
  • Fundamentally Energy-Efficient Architectures
  • Memory-centric (Data-centric) Architectures
  • Fundamentally Low-Latency Architectures
  • Architectures for Genomics, Medicine, Health
  • Genome Sequence Analysis
  • Reference Genome
  • Read Mapping
  • Read Alignment/Verification
  • Edit Distance
  • In-Memory DNA Sequence Analysis
  • Memory Bottleneck
  • Main Memory
  • Storage (SSD/HDD)
  • The Memory Capacity Gap
  • DRAM Capacity, Bandwidth & Latency
  • Flash Memory
  • RowHammer
  • Non-Volatile Memory (NVM) (e.g., PCM, STTRAM, ReRAM, 3D Xpoint)
  • Emerging Memory Technologies
  • 3D-Stacked DRAM
  • Hybrid Main Memory
  • System-Memory Co-Design
  • Microarchitecture
  • Memory-Centric System Design
  • Memory Interference
  • Memory Controllers

Lecture 3c (07.10 Thu.)

  • Levels of transformation
  • Abstraction layers
  • Multi-core systems
  • Single-core
  • Interface
  • DRAM
  • Caches
  • Memory controller
  • Parallel processing
  • GPU
  • Slowdown
  • Quality of service
  • DRAM Bank
  • Row buffer
  • Row hit/miss
  • FR-FCFS
  • DRAM scheduling
  • Random memory accesses
  • Sequential memory accesses
  • Memory performance hog
  • Compiler

Lecture 4a (08.10 Fri.)

  • Memory QoS
  • Memory performance attacks
  • Abstraction layers
  • Multi core systems
  • Interference
  • Memory system problem
  • Memory performance hog
  • Cloud computing
  • Automotive systems
  • QoS guarantees
  • Equal slowdown
  • Fairness
  • Round-Robin
  • DRAM bank
  • DRAM sub-array
  • Sense amplifier
  • DRAM sensing
  • Memory controller
  • DRAM row activation
  • Row decoder
  • Row buffer
  • Row buffer hit
  • Row buffer conflict
  • Cache block
  • DRAM chip
  • DRAM burst
  • FR-FCFS
  • Machine learning based memory controller
  • DRAM throughput
  • Denial of service attack
  • Streaming benchmark
  • Cache line size
  • Rando access pattern
  • Memory intensity
  • Memory controller policy
  • Machine learning
  • Reinforcement learning
  • Neural networks
  • Slowdown
  • Zurich airport
  • Memory channel partitioning
  • Load balance
  • Router
  • Packet switching
  • Interconnect
  • Abstraction layer
  • Slow down estimation
  • Branch prediction
  • Complexity

Lecture 4b (08.10 Fri.)

  • Data retention
  • Retention failure
  • Refresh
  • Charge
  • Capacitor
  • Charge base memory
  • Charge leakage
  • Refresh granularity
  • Exabyte
  • Profiling
  • Bit error rate
  • Manufacturing variations
  • Leaky cell
  • Process variation
  • Retention time
  • DRAM module
  • Data allocation
  • Virtual memory
  • Operating system
  • Physical page
  • Virtual page
  • Implementation
  • FPGA board
  • Samsung DRAM chip
  • Refresh interval
  • Bloom filter
  • Simulation
  • Performance improvement
  • Technology node
  • Chip density
  • Memory bandwidth bottleneck
  • Robustness
  • Data pattern dependence
  • Variable retention time
  • Bitline
  • Wordline
  • Bitline-Bitline coupling
  • Wrodline-Wordline coupling
  • Physical adjacency
  • Worst case data pattern
  • Worst case retention time
  • Adjacent cell
  • Reverse engineering
  • Temparature range
  • Retention time profile
  • ECC
  • Low retention state
  • High retention state
  • DRAM reliability and security
  • Exploit
  • Set membership
  • Probabilistic data structure
  • Element
  • Mapping
  • Bin
  • Hash function
  • Hash coding
  • Correctness
  • Low hanging fruit
  • Application behavior

Lecture 5 (14.10 Thu.)

  • RowHammer
  • Secure/Reliable/Safe Architectures
  • Intelligent Memory Controller
  • TRR-protected DRAM chip
  • Many-sided RowHammer attack
  • DDR
  • Aggressor row
  • In-DRAM TRR
  • Sampler
  • Inhibitor
  • In-DRAM ECC
  • Cold boot attacks
  • Double-sided RowHammer
  • SECDED
  • memtest86
  • Dense DRAM chip
  • RowHammer mitigation mechanism
  • Vulnerable chip
  • RowHammer characterization
  • RowHammer vulnerability
  • DRAM testing infrastructure
  • DDR3
  • DDR4
  • LPDDR4
  • DRAM refresh
  • DRAM calibration event
  • Refresh window
  • Retention failure
  • Aggressor Row
  • Victim Row
  • Data pattern
  • Hammer Count
  • RowHammer bit flip rate
  • Technology node generation
  • Row Distance
  • DRAM-system cooperation
  • Profiling mechanism
  • Security
  • Safety
  • Bit flip
  • Maslow Hierarchy
  • Charge-based memory
  • Data retention
  • Flash memory
  • Disturbance errors
  • Hammered row
  • Victim row
  • Electrical interference
  • Security attack
  • kernel privileges
  • Page Table Entry (PTE)
  • Electromagnetic coupling
  • Aggressor row
  • Refresh rate
  • Data pattern
  • Victim cells
  • Weak cells
  • ECC
  • Variable retention time
  • Rowhammer solutions
  • PARA (Probabilistic Adjacent Row Activation)
  • RowHammer mitigation

Lecture 6 (15.10 Fri.)

  • DRAM reliability
  • Flash memory
  • NAND flash vulnerabilities/reliability
  • Retention errors
  • Data Pattern Dependence (DPD)
  • Variable Retention Time (VRT)
  • Byzantine failure
  • In-memory Computation/Processing
  • Processing in Memory (PIM)
  • Near-data Processing (NDP)
  • Data movement
  • Maslow's (Human) Hierarchy of Needs
  • Intelligent controllers
  • Processing using Memory
  • Processing near Memory
  • Bulk data copy/initialization
  • In-DRAM row copy
  • RowClone
  • Subarray
  • Banks

Lecture 7 (21.10 Thu.)

  • Data Movement
  • Processing in memory (PIM)
  • In-memory computation/processing
  • Near-data processing (NDP)
  • UPMEM Processing-in-DRAM Engine
  • 3D-stacked memory
  • RowClone
  • Gather/Scatter DRAM
  • Bulk data copy and initialization
  • In-Memory copy
  • Intra-subarray
  • Inter-bank
  • Memory as an accelerator
  • Low-cost Inter-linked subarrays (LISA)
  • Fine-Grained In-DRAM Copy (FIGARO)
  • Network-On-Memory
  • Bulk Bitwise in-DRAM Computation (Ambit)
  • Intelligent Memory Device
  • ComputeDRAM
  • Dual Contact Cell
  • New memory technologies

Lecture 8 (22.10 Fri.)

  • Near-Data Processing
  • 3D-Stacked Logic+Memory
  • In-Memory Graph Processing
  • Tesseract
  • Consumer Devices
  • Data Movement Bottleneck
  • TensorFlow Mobile
  • Chrome Browser
  • Video Playback and Capture
  • GPU Processing
  • Transparent Offloading and Mapping (TOM)
  • Climate Modeling
  • Approximate String Matching
  • Time Series Analysis
  • PIM-Enabled Instructions
  • Simple PIM Operations
  • Code and Data Mapping
  • Data Coherence Support
  • Minimal Data Movement
  • Genome Read In-Memory (GRIM) Filter
  • UPMEM
  • Principle Design

Lecture 9 (28.10 Thu.)

  • Processing in Memory
  • Real world PIM architecture
  • Accelerator model
  • UPMEM DIMM
  • DPU
  • Tasklet
  • Parallel Reduction
  • Data Movement
  • Processing in memory (PIM)
  • In-memory computation/processing
  • Near-data processing (NDP)
  • UPMEM Processing-in-DRAM Engine
  • 3D-stacked memory
  • RowClone
  • Gather/Scatter DRAM
  • Bulk data copy and initialization
  • In-Memory copy
  • Intra-subarray
  • Inter-bank
  • Memory as an accelerator
  • Weak scaling
  • strong scaling
  • PrIM
  • MRAM, WRAM
  • DAMOV
  • Locality-Based Clustering
  • Memory Bottleneck Analysis

Lecture 10 (29.10 Fri.)

  • Genome analysis
  • DNA
  • Cell information
  • Genetic content
  • Human genome
  • DNA genotypes
  • Personalized Medicine
  • Intelligent Genome Analysis
  • SARS-CoV-2
  • Privacy-Preserving Genome Analysis
  • RNA
  • Nanopore
  • Protein / Phenotypes
  • Adenine (A), Thymine (T), Guanine (G), Cytosine (C)
  • Supercoiled
  • Chromosomes
  • HeLa's cells (Henrietta Lacks)
  • Reference genome
  • Sequence alignment
  • High-throughput sequencing (HTS)
  • Read mapping
  • Indexing
  • Hashing
  • Smith-Waterman
  • Hamming distance
  • Metagenomics Analysis
  • Hash based seed-and-extend
  • K-mers
  • Burrows-Wheeler Transform
  • Ferragina-Manzini Index
  • Edit distance
  • Match / Mismatch
  • Deletion / Insertion / Substitution
  • Dynamic programming
  • MrFAST
  • Verification
  • Seed filtering
  • Needleman-Wunsch
  • Hardware Acceleration for genomic analysis
  • Accelerating Read Mapping
  • Seed Filtering
  • Pre-alignment Filtering
  • Read Alignment Acceleration
  • GRIM-Filter
  • GenASM
  • SneakySnake
  • GateKeeper
  • MAGNET
  • Shouji
  • GateKeeper-GPU
  • SneakySnake
  • FastHash
  • Adjacent k-mers
  • Adjacency filtering
  • Cheap k-mer selection
  • Pre-alignment filtering
  • Hamming distance
  • Shifted Hamming distance
  • FPGA
  • Data movement bottleneck
  • processing-in-memory
  • processing-using-memory
  • processing-near-memory
  • Near-memory Pre-alignment Filtering
  • 3D-Stacked DRAM
  • GenCache
  • AirLift

Lecture 11 (4.11 Thu.)

  • Maslow’s Hierarchy
  • Low latency
  • Memory bottleneck
  • Data-centric (Memory-centric) architectures
  • DRAM
  • DDR3
  • 3D-Stacked DRAM
  • Runahed Execution
  • Sense Amplifier
  • DRAM cell
  • DRAM bank
  • DRAM chip
  • Tiered Latency DRAM
  • Variable Latency DRAM
  • CROW (The Copy Row Substrate)
  • CLR-DRAM
  • SALP
  • Global Row-buffer
  • Local Row-buffer
  • Timing margins
  • Process variation
  • Worst-case
  • Adaptive-latency
  • DRAM characterization
  • SoftMC
  • Restore time
  • AL-DRAM
  • Latency variation
  • Flexible-Latency DRAM
  • Solar DRAM
  • Physical Unclonable Function (PUF)
  • True Random Number Generator
  • Refresh Latency
  • ChargeCache
  • Vampire DRAM

Lecture 12a (5.11 Fri.)

  • Low latency
  • Memory bottleneck
  • Data-centric (Memory-centric) architectures
  • DRAM
  • Runahead Execution
  • Sense Amplifier
  • DRAM cell
  • DRAM bank
  • DRAM chip
  • Tiered Latency DRAM
  • Variable Latency DRAM
  • CLR-DRAM
  • SALP
  • Global Row-buffer
  • Local Row-buffer
  • Timing margins
  • Process variation
  • Worst-case
  • Adaptive-latency
  • DRAM characterization
  • SoftMC
  • Restore time
  • AL-DRAM
  • Latency variation
  • Flexible-Latency DRAM
  • Solar DRAM
  • Physical Unclonable Function (PUF)
  • True Random Number Generator
  • Refresh Latency
  • ChargeCache
  • Vampire DRAM
  • Memory Controller
  • DRAM Latency
  • DRAM Throughput
  • Phase Change Memory
  • Spin-Transfer Torque Magnetic Memory
  • Flash Memory
  • Solid-State Drive (SSD)
  • SSD Controller
  • Error-Correcting Code (ECC)
  • Wear Leveling
  • Garbage Collection
  • Voltage Optimization
  • Page Remapping
  • DRAM Types
  • DDR (Double Data Rate)
  • LPDDR (Low-Power DDR)
  • GDDR (Graphic DDR for High Bandwidth)
  • eDRAM (Enhanced DRAM)
  • RLDRAM (Reduced-Latency DRAM)
  • Ramulator
  • DRAM Controller
  • DRAM Request
  • Request Buffer
  • FCFS (First Come First Served)
  • FR-FCFS (first Ready, First Come First Served)
  • Row Buffer Management Policy
  • Open-Row Policy
  • Closed-Row Policy
  • DRAM Power Management
  • DRAM Timing Constraints
  • DRAM Refresh
  • Quality of Service (QoS)
  • Memory Contention
  • Subarray-Level Parallelism
  • Main Memory Interference

Lecture 12b (5.11 Fri.)

  • Self-Optimizing DRAM Controller
  • Reinforcement Learning
  • Self-Optimizing Computing Architecture
  • Data-Driven Computing Architecture
  • Intelligent Architectures
  • Deep neural networks (DNN)
  • DNN training
  • DNN inference
  • DNN Weights
  • Retraining
  • DNN Accuracy
  • FCFS (First Come First Served)
  • FR-FCFS (first Ready, First Come First Served)
buzzword.1636297729.txt.gz · Last modified: 2021/11/07 15:08 by kanellok