buzzword
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| buzzword [2021/12/02 14:55] – [Lecture 17b (25.11 Thu.)] mnika | buzzword [2022/01/03 11:06] (current) – loisor | ||
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| * Banks | * Banks | ||
| - | ==== Lecture 7 (21.10 Thu.) ==== | + | ===== Lecture 7 (21.10 Thu.) ===== |
| *Data Movement | *Data Movement | ||
| *Processing in memory (PIM) | *Processing in memory (PIM) | ||
| Line 746: | Line 746: | ||
| * Analog to Digital Converter (ADC) | * Analog to Digital Converter (ADC) | ||
| * NVM-based PIM system | * NVM-based PIM system | ||
| + | |||
| + | ===== Lecture 16a (19.11 Fri.) ===== | ||
| + | * RowHammer Vulnerability | ||
| + | * RowHammer Protection | ||
| + | * DRAM | ||
| + | * Target Row Buffer (TRR) | ||
| + | * Data retention failure | ||
| + | * DRAM Refresh | ||
| + | * Bit flip | ||
| + | * Aggressor row | ||
| + | * U-TTR | ||
| + | * Row Scout | ||
| + | * TRR Analyzer | ||
| + | * Retention time | ||
| + | * DRAM Access pattern | ||
| + | * SoftMC | ||
| + | * FPGA | ||
| + | * TREF | ||
| + | * Dummy row hammer | ||
| + | * ECC | ||
| + | * Memory Controller | ||
| + | |||
| + | ===== Lecture 16b (19.11 Fri.) ===== | ||
| + | |||
| + | * RowHammer | ||
| + | * DRAM | ||
| + | * Activate | ||
| + | * Precharge | ||
| + | * Temperature | ||
| + | * Aggressor Row Active Time | ||
| + | * Victim Cell | ||
| + | * Physical Location | ||
| + | * SoftMC | ||
| + | * FPGA | ||
| + | * DRAM Refresh | ||
| + | * Bit flips | ||
| + | * Variation | ||
| + | * Spatial variation across columns | ||
| + | * RowHammer attacks | ||
| + | * RowHammer defences | ||
| + | |||
| + | ===== Lecture 16c (19.11 Fri.) ===== | ||
| + | |||
| + | * RowHammer | ||
| + | * Preventing RowHammer | ||
| + | * DRAM | ||
| + | * Bit flip | ||
| + | * DRAM Refresh | ||
| + | * Activate | ||
| + | * Precharge | ||
| + | * Physical isolation | ||
| + | * Reactive refresh | ||
| + | * Proactive throttling | ||
| + | * Scalability | ||
| + | * Compatibility | ||
| + | * Victim row | ||
| + | * Aggressor row | ||
| + | * RowBlocker | ||
| + | * Bloom filter | ||
| + | * AttackThrottler | ||
| + | |||
| + | ===== Lecture 16d (19.11 Fri.) ===== | ||
| + | |||
| + | * DRAM | ||
| + | * On-die ECC | ||
| + | * Memory error | ||
| + | * Data retention | ||
| + | * Write recovery | ||
| + | * Variable retention time | ||
| + | * Single-bit errors | ||
| + | * ECC encoder | ||
| + | * ECC decoder | ||
| + | * Error profile | ||
| + | * Error-prone data store | ||
| + | * Uncorrectable error | ||
| + | * At-risk bits | ||
| + | * Data patterns | ||
| + | * Memory controller | ||
| + | * Monte-carlo simulation | ||
| + | * Data retention | ||
| + | |||
| ===== Lecture 17a (25.11 Thu.) ===== | ===== Lecture 17a (25.11 Thu.) ===== | ||
| Line 906: | Line 987: | ||
| * Dataflow processor | * Dataflow processor | ||
| + | |||
| + | ===== Lecture 20 (03.12 Fri.) ===== | ||
| + | |||
| + | * Cache coherence | ||
| + | * Memory consistency | ||
| + | * Shared memory model | ||
| + | * Software coherence | ||
| + | * Coarse-grained (page-level) | ||
| + | * Non-cacheable | ||
| + | * Fine-grained (cache flush) | ||
| + | * Hardware coherence | ||
| + | * Valid/ | ||
| + | * Write propagation | ||
| + | * Write serialization | ||
| + | * Update vs. Invalid | ||
| + | * Snoopy bus | ||
| + | * Directory | ||
| + | * Exclusive bit | ||
| + | * Directory optimizations (bypassing) | ||
| + | * Snoopy cache | ||
| + | * Shared bus | ||
| + | * VI protocol | ||
| + | * MSI (Modified, Shared, Invalid) | ||
| + | * Exclusive state | ||
| + | * MESI (Modified, Exclusive, Shared, Invalid) | ||
| + | * Illinois Protocol (MESI) | ||
| + | * Broadcast | ||
| + | * Bus request | ||
| + | * Downgrade/ | ||
| + | * Snoopy invalidation | ||
| + | * Cache-to-cache transfer | ||
| + | * Writeback | ||
| + | * MOESI (Modified, Owned, Exclusive, Shared, Invalid) | ||
| + | * Directory coherence | ||
| + | * Race conditions | ||
| + | * Totally-ordered interconnect | ||
| + | * Directory-based protocols | ||
| + | * Set inclusion test | ||
| + | * Linked list | ||
| + | * Bloom filters | ||
| + | * Contention resolution | ||
| + | * Ping-ponging | ||
| + | * Synchronization | ||
| + | * Shared-data-structure | ||
| + | * Token Coherence | ||
| + | * Coherence for NDAs | ||
| + | * Optimistic execution | ||
| + | * Signature | ||
| + | * Commit/ | ||
| + | |||
| + | ===== Lecture 21 (09.12 Thu.) ===== | ||
| + | * Interconnects | ||
| + | * Cache coherence | ||
| + | * Interconnect networks: | ||
| + | * Topology | ||
| + | * Routing | ||
| + | * Buffering and flow control | ||
| + | * Oversubscription of routers | ||
| + | * Terminology: | ||
| + | * Network Interface | ||
| + | * Link | ||
| + | * Switch/ | ||
| + | * Channel | ||
| + | * Node | ||
| + | * Message | ||
| + | * Packet | ||
| + | * Flit | ||
| + | * Direct/ | ||
| + | * Properties of a Network Topology: | ||
| + | * Regular/ | ||
| + | * Routing distance | ||
| + | * Diameter | ||
| + | * Average distance | ||
| + | * Bisection Bandwidth | ||
| + | * Blocking/ | ||
| + | * Topologies: | ||
| + | * Bus | ||
| + | * P2P | ||
| + | * Crossbar | ||
| + | * Ring | ||
| + | * Tree | ||
| + | * Omega | ||
| + | * Hypercube | ||
| + | * Mesh | ||
| + | * Torus | ||
| + | * Butterfly | ||
| + | * cost, latency, contention, energy, bandwidth, overall performance | ||
| + | * Circuit switching network | ||
| + | * Multistage network | ||
| + | * Fetch-and-add | ||
| + | * Unidirectional Ring | ||
| + | * Bidirectional rings | ||
| + | * Hierarchical rings | ||
| + | * Mesh: asymmetricity on the edge | ||
| + | * Torus | ||
| + | * H-tree | ||
| + | * Fat-tree | ||
| + | * Hyper-cube. Cosmic Cube | ||
| + | * Routing mechanism: Arithmetic, Source-based, | ||
| + | * Types of routing algorithm: deterministic, | ||
| + | * Deadlock | ||
| + | * Oblivious routing | ||
| + | * Adaptive Routing: minimal adaptive, non-minimal adaptive | ||
| + | * Flow Control | ||
| + | * Handling contention: buffer, drop or misroute | ||
| + | * Flow control methods: | ||
| + | * Circuit switching | ||
| + | * Bufferless | ||
| + | * Store and forward | ||
| + | * Virtual cut through | ||
| + | * Wormhole | ||
| + | * Performance and congestion at high loads | ||
| + | * Store-and-forward | ||
| + | * Cut-though flow control | ||
| + | * Wormhole flow control | ||
| + | * Head of Line Blocking | ||
| + | * Virtual Channel Flow Control | ||
| + | |||
| + | ===== Lecture 22 (10.12 Fri.) ===== | ||
| + | * Load latency curve | ||
| + | * Ideal latency | ||
| + | * Manhattan distance | ||
| + | * Bit-Compliment traffic | ||
| + | * Uniform Random traffic | ||
| + | * Transpose traffic | ||
| + | * Adaptive topology | ||
| + | * Performance of interconnection networks | ||
| + | * On-chip networks | ||
| + | * Difference between off-chip and on-chip networks | ||
| + | * Network buffers | ||
| + | * Efficient routing | ||
| + | * Advantages of on-chip interconnects | ||
| + | * Saturation throughput | ||
| + | * Pin constraints | ||
| + | * Wiring resources | ||
| + | * Disadvantages of on-chip interconnects | ||
| + | * Energy/ | ||
| + | * Tradeoffs of interconnect design | ||
| + | * Buffers in NoC routers | ||
| + | * Bufferless routing | ||
| + | * Flit-level routing | ||
| + | * Deflection routing | ||
| + | * Age-Based prioritization | ||
| + | * Buffer and link energy consumption | ||
| + | * Self-throttling | ||
| + | * Livelock freedom problem | ||
| + | * Golden packet for livelock freedom | ||
| + | * Reassembly buffers | ||
| + | * Performance-Power Spectrum | ||
| + | * Packet retransmission | ||
| + | * Packet scheduling | ||
| + | |||
| + | ===== Lecture 23 (16.12 Thu.) ===== | ||
| + | * SIMD | ||
| + | * SISD | ||
| + | * MISD | ||
| + | * Systolic arrays | ||
| + | * MIMD | ||
| + | * Instruction level parallelism (ILP) | ||
| + | * Array processor | ||
| + | * Vector processor | ||
| + | * VLIW: Very long instruction word | ||
| + | * Vector length register (VLEN) | ||
| + | * Vector stride register (VSTR) | ||
| + | * Vector load instruction (VLD) | ||
| + | * Intra-vector dependencies | ||
| + | * Regular parallelism | ||
| + | * Memory bandwidth | ||
| + | * Vector data register | ||
| + | * Vector control registers | ||
| + | * Vector mask register | ||
| + | * Vector functional units | ||
| + | * Vector registers | ||
| + | * VADD | ||
| + | * Scalar operations | ||
| + | * Memory data register | ||
| + | * Memory address register | ||
| + | * Interleaved memory | ||
| + | * Memory banking | ||
| + | * Address generator | ||
| + | * Monolithic memory | ||
| + | * Memory access latency | ||
| + | * Vectorizable loops | ||
| + | * Vector code performance | ||
| + | * Vector data forwarding (chaining) | ||
| + | * Vector chaining | ||
| + | * Vector stripmining | ||
| + | * Irregular memory access | ||
| + | * Gather/ | ||
| + | * Sparse vector | ||
| + | * Masked operations | ||
| + | * Predicated execution | ||
| + | * Row/Column major layouts | ||
| + | * Bank conflicts | ||
| + | * Randomized mapping | ||
| + | * Vector instruction level parallelism | ||
| + | * Automatic code vectorization | ||
| + | * Packed arithmetic | ||
| + | * GPUs | ||
| + | * Programming model vs execution model | ||
| + | * SPMD | ||
| + | * Warp (wavefront) | ||
| + | * SIMD vs. SIMT | ||
| + | * Warp-level FGMT | ||
| + | * Vector lanes | ||
| + | * Warp scheduler | ||
| + | * Fine-grained multithreading | ||
| + | * Warp instruction level parallelism | ||
| + | * Warp-based SIMD vs. traditional SIMD | ||
| + | * Multiple instruction streams | ||
| + | * Conditional control flow instructions | ||
| + | * Branch divergence | ||
| + | * Dynamic warp formation | ||
| + | * Functional unit | ||
buzzword.1638456920.txt.gz · Last modified: 2021/12/02 14:55 by mnika