buzzword
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| buzzword [2021/12/12 17:35] – azizibar | buzzword [2022/01/03 11:06] (current) – loisor | ||
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| * Banks | * Banks | ||
| - | ==== Lecture 7 (21.10 Thu.) ==== | + | ===== Lecture 7 (21.10 Thu.) ===== |
| *Data Movement | *Data Movement | ||
| *Processing in memory (PIM) | *Processing in memory (PIM) | ||
| Line 746: | Line 746: | ||
| * Analog to Digital Converter (ADC) | * Analog to Digital Converter (ADC) | ||
| * NVM-based PIM system | * NVM-based PIM system | ||
| + | |||
| + | ===== Lecture 16a (19.11 Fri.) ===== | ||
| + | * RowHammer Vulnerability | ||
| + | * RowHammer Protection | ||
| + | * DRAM | ||
| + | * Target Row Buffer (TRR) | ||
| + | * Data retention failure | ||
| + | * DRAM Refresh | ||
| + | * Bit flip | ||
| + | * Aggressor row | ||
| + | * U-TTR | ||
| + | * Row Scout | ||
| + | * TRR Analyzer | ||
| + | * Retention time | ||
| + | * DRAM Access pattern | ||
| + | * SoftMC | ||
| + | * FPGA | ||
| + | * TREF | ||
| + | * Dummy row hammer | ||
| + | * ECC | ||
| + | * Memory Controller | ||
| + | |||
| + | ===== Lecture 16b (19.11 Fri.) ===== | ||
| + | |||
| + | * RowHammer | ||
| + | * DRAM | ||
| + | * Activate | ||
| + | * Precharge | ||
| + | * Temperature | ||
| + | * Aggressor Row Active Time | ||
| + | * Victim Cell | ||
| + | * Physical Location | ||
| + | * SoftMC | ||
| + | * FPGA | ||
| + | * DRAM Refresh | ||
| + | * Bit flips | ||
| + | * Variation | ||
| + | * Spatial variation across columns | ||
| + | * RowHammer attacks | ||
| + | * RowHammer defences | ||
| + | |||
| + | ===== Lecture 16c (19.11 Fri.) ===== | ||
| + | |||
| + | * RowHammer | ||
| + | * Preventing RowHammer | ||
| + | * DRAM | ||
| + | * Bit flip | ||
| + | * DRAM Refresh | ||
| + | * Activate | ||
| + | * Precharge | ||
| + | * Physical isolation | ||
| + | * Reactive refresh | ||
| + | * Proactive throttling | ||
| + | * Scalability | ||
| + | * Compatibility | ||
| + | * Victim row | ||
| + | * Aggressor row | ||
| + | * RowBlocker | ||
| + | * Bloom filter | ||
| + | * AttackThrottler | ||
| + | |||
| + | ===== Lecture 16d (19.11 Fri.) ===== | ||
| + | |||
| + | * DRAM | ||
| + | * On-die ECC | ||
| + | * Memory error | ||
| + | * Data retention | ||
| + | * Write recovery | ||
| + | * Variable retention time | ||
| + | * Single-bit errors | ||
| + | * ECC encoder | ||
| + | * ECC decoder | ||
| + | * Error profile | ||
| + | * Error-prone data store | ||
| + | * Uncorrectable error | ||
| + | * At-risk bits | ||
| + | * Data patterns | ||
| + | * Memory controller | ||
| + | * Monte-carlo simulation | ||
| + | * Data retention | ||
| + | |||
| ===== Lecture 17a (25.11 Thu.) ===== | ===== Lecture 17a (25.11 Thu.) ===== | ||
| Line 1025: | Line 1106: | ||
| ===== Lecture 22 (10.12 Fri.) ===== | ===== Lecture 22 (10.12 Fri.) ===== | ||
| - | * | ||
| * Load latency curve | * Load latency curve | ||
| * Ideal latency | * Ideal latency | ||
| Line 1058: | Line 1138: | ||
| * Packet retransmission | * Packet retransmission | ||
| * Packet scheduling | * Packet scheduling | ||
| + | |||
| + | ===== Lecture 23 (16.12 Thu.) ===== | ||
| + | * SIMD | ||
| + | * SISD | ||
| + | * MISD | ||
| + | * Systolic arrays | ||
| + | * MIMD | ||
| + | * Instruction level parallelism (ILP) | ||
| + | * Array processor | ||
| + | * Vector processor | ||
| + | * VLIW: Very long instruction word | ||
| + | * Vector length register (VLEN) | ||
| + | * Vector stride register (VSTR) | ||
| + | * Vector load instruction (VLD) | ||
| + | * Intra-vector dependencies | ||
| + | * Regular parallelism | ||
| + | * Memory bandwidth | ||
| + | * Vector data register | ||
| + | * Vector control registers | ||
| + | * Vector mask register | ||
| + | * Vector functional units | ||
| + | * Vector registers | ||
| + | * VADD | ||
| + | * Scalar operations | ||
| + | * Memory data register | ||
| + | * Memory address register | ||
| + | * Interleaved memory | ||
| + | * Memory banking | ||
| + | * Address generator | ||
| + | * Monolithic memory | ||
| + | * Memory access latency | ||
| + | * Vectorizable loops | ||
| + | * Vector code performance | ||
| + | * Vector data forwarding (chaining) | ||
| + | * Vector chaining | ||
| + | * Vector stripmining | ||
| + | * Irregular memory access | ||
| + | * Gather/ | ||
| + | * Sparse vector | ||
| + | * Masked operations | ||
| + | * Predicated execution | ||
| + | * Row/Column major layouts | ||
| + | * Bank conflicts | ||
| + | * Randomized mapping | ||
| + | * Vector instruction level parallelism | ||
| + | * Automatic code vectorization | ||
| + | * Packed arithmetic | ||
| + | * GPUs | ||
| + | * Programming model vs execution model | ||
| + | * SPMD | ||
| + | * Warp (wavefront) | ||
| + | * SIMD vs. SIMT | ||
| + | * Warp-level FGMT | ||
| + | * Vector lanes | ||
| + | * Warp scheduler | ||
| + | * Fine-grained multithreading | ||
| + | * Warp instruction level parallelism | ||
| + | * Warp-based SIMD vs. traditional SIMD | ||
| + | * Multiple instruction streams | ||
| + | * Conditional control flow instructions | ||
| + | * Branch divergence | ||
| + | * Dynamic warp formation | ||
| + | * Functional unit | ||
buzzword.1639330518.txt.gz · Last modified: 2021/12/12 17:35 by azizibar