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readings
Table of Contents
Readings
Guides on how to review papers critically
Lecture 1 (23.09 Thu.)
Lecture 2 (01.10 Fri.)
Lecture 3a (07.10 Thu.)
Lecture 3c (07.10 Thu.)
Lecture 4a (08.10 Fri.)
Lecture 4b (08.10 Fri.)
Lecture 5 (14.10 Thu.)
Lecture 6a (15.10 Thu.)
Lecture 6b (15.10 Thu.)
Lecture 7 (21.10 Thu.)
Lecture 8 (22.10 Fri.)
Lecture 9 (28.10 Thu.)
Lecture 10 (29.10 Fri.)
Lecture 11 (4.11 Thu.)
Lecture 12a (5.11 Fri.)
Lecture 12b (5.11 Fri.)
Lecture 13 (11.11 Thu.)
Lecture 14a (12.11 Fri.)
Lecture 14b (12.11 Fri.)
Lecture 15a (18.11 Thu.)
Lecture 15b (18.11 Thu.)
Lecture 15c (18.11 Thu.)
Lecture 16a (19.11 Fri.)
Lecture 16b (19.11 Fri.)
Lecture 16c (19.11 Fri.)
Lecture 16d (19.11 Fri.)
Lecture 17a (25.11 Fri.)
Lecture 17b (25.11 Fri.)
Lecture 18 (26.11 Fri.)
Lecture 19a (2.12 Thu.)
Lecture 19b (2.12 Thu.)
Lecture 20 (3.12 Fri.)
Lecture 21 (09.12 Thu.)
Lecture 22 (10.12 Fri.)
Lecture 23 (16.12 Fri.)
Lecture 24a (23.12 Thu.)
Lecture 24b (23.12 Thu.)
Lecture 24c (23.12 Thu.)
Lecture 24d (23.12 Thu.)
Readings
Guides on how to review papers critically
Guidelines on how to do paper reviews
Video
Lecture slides:
PDF
PPT
Example reviews on “Main Memory Scaling: Challenges and Solution Directions”
(link to the paper)
Review 1
Review 2
Example review on “Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems”
(link to the paper)
Review 1
Guidelines on How to Deliver Paper Review Presentations
Video
Lecture 1 (23.09 Thu.)
Required Readings (Lecture 1)
R.W. Hamming, "You and Your Research", Transcription of the Bell Communications Research Colloquium Seminar, 1986
YouTube: Video Recording of Richard Hamming delivering the talk "You and Your Research" (June 6, 1995)
Mentioned Readings and Talks (Lecture 1)
O. Mutlu, "SAFARI Research Group: Introduction & Research", Talk at ETH Future Computing Laboratory Welcome Workshop (EFCL), Virtual, 6 July 2021.
O. Mutlu, "Some Reflections (on DRAM)", Award Speech for ACM SIGARCH Maurice Wilkes Award, at the ISCA Awards Ceremony, Phoenix, AZ, USA, 25 June 2019.
Video of Award Acceptance Speech (13 minutes)
Video of Interview after Award Acceptance (1 hour 6 minutes)
Article: "ACM SIGARCH Maurice Wilkes Award goes to Prof. O. Mutlu"
O. Mutlu, "How to Build an Impactful Research Group", 57th Design Automation Conference Early Career Workshop (DAC), Virtual, 19 July 2020.
O. Mutlu, "Computer Architecture: Why Is It So Important and Exciting Today?", Invited Lecture at Izmir Institute of Technology (IYTE), Virtual, 16 October 2020.
Video (2 hours 12 minutes)
O. Mutlu, "Applying to Graduate School & Doing Impactful Research", Invited Panel Talk at the 3rd Undergraduate Mentoring Workshop, held with the 48th International Symposium on Computer Architecture (ISCA), Virtual, 18 June 2021.
Video (50 minutes)
Jouppi et al., “In-Datacenter Performance Analysis of a Tensor Processing Unit”, ISCA 2017.
Mohammed Alser, Zülal Bingöl, Damla Senol Cali, Jeremie Kim, Saugata Ghose, Can Alkan, Onur Mutlu “Accelerating Genome Analysis: A Primer on an Ongoing Journey” IEEE Micro, August 2020.
Juan Gómez-Luna, Izzat El Hajj, Ivan Fernandez, Christina Giannoula, Geraldo F. Oliveira, Onur Mutlu. "Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture".
Video (2 hours 57 minutes)
S. Koppula, L. Orosa, A. G. Yaglikci, R. Azizi, T. Shahroodi, K. Kanellopoulos, and O. Mutlu, "EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM," MICRO, 2019
K. Kanellopoulos, N. Vijaykumar, C. Giannoula, R. Azizi, S. Koppula, N. M. Ghiasi, T. Shahroodi, J. Gomez-Luna, and O. Mutlu, "SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations", MICRO, 2019
Damla Senol Cali, Gurpreet S. Kalsi, Zulal Bingol, Can Firtina, Lavanya Subramanian, Jeremie S. Kim, Rachata Ausavarungnirun, Mohammed Alser, Juan Gomez-Luna, Amirali Boroumand, Anant Nori, Allison Scibisz, Sreenivas Subramoney, Can Alkan, Saugata Ghose, and Onur Mutlu, "GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis," MICRO, 2020
G. Singh, D. Diamantopoulos, C. Hagleitner, J. Gómez-Luna, S. Stuijk, O. Mutlu, and H. Corporaal, "NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling," FPL, 2020
I. Fernandez, R. Quislant, C. Giannoula, M. Alser, J. Gómez-Luna, E. Gutiérrez, O. Plata, and O. Mutlu, "NATSA: A Near-Data Processing Accelerator for Time Series Analysis," ICCD, 2020
G. Singh, M. Alser, D.S. Cali, D. Diamantopoulos, J. Gómez-Luna, H. Corporaal, and O. Mutlu, "FPGA-based Near-Memory Acceleration of Modern Data-Intensive Applications". IEEE Micro (IEEE MICRO), 2021.
Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, "A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing," ISCA, 2015.
A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan, and O. Mutlu, "Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,” ASPLOS, 2018.
Kevin Hsieh, Samira Khan, Nandita Vijaykumar, Kevin K. Chang, Amirali Boroumand, Saugata Ghose, and Onur Mutlu, "Accelerating Pointer Chasing in 3D-Stacked Memory: Challenges, Mechanisms, Evaluation," ICCD, 2016.
Nandita Vijaykumar, Abhilasha Jain, Diptesh Majumdar, Kevin Hsieh, Gennady Pekhimenko, Eiman Ebrahimi, Nastaran Hajinazar, Phillip B. Gibbons, Onur Mutlu, "A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap with Expressive Memory", ISCA 2018.
Nandita Vijaykumar, Eiman Ebrahimi, Kevin Hsieh, Phillip B. Gibbons and Onur Mutlu, "The Locality Descriptor: A Holistic Cross-Layer Abstraction to Express Data Locality in GPUs" Proceedings of the 45th International Symposium on Computer Architecture (ISCA), Los Angeles, CA, USA, June 2018.
Yixin Luo, Sriram Govindan, Bikash Sharma, Mark Santaniello, Justin Meza, Aman Kansal, Jie Liu, Badriddine Khessib, Kushagra Vaid, and Onur Mutlu, "Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory" DSN 2014
Nastaran Hajinazar, Pratyush Patel, Minesh Patel, Konstantinos Kanellopoulos, Saugata Ghose, Rachata Ausavarungnirun, Geraldo Francisco de Oliveira Jr., Jonathan Appavoo, Vivek Seshadri, and Onur Mutlu, "The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework," In ISCA, 2020
B.C. Lee, E. Ipek, O. Mutlu, D. Burger, "Architecting Phase Change Memory as a Scalable DRAM Alternative," ISCA 2009
B. C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. Burger "Phase-Change Technology and the Future of Main Memory" IEEE Micro Top Picks 2010
Young-Cheon Kwon, Suk Han Lee, Jaehoon Lee, Sang-Hyuk Kwon, Je Min Ryu, Jong-Pil Son, Seongil O, Hak-Soo Yu, Haesuk Lee, Soo Young Kim, Youngmin Cho, Jin Guk Kim, Jongyoon Choi, Hyun-Sung Shin, Jin Kim, BengSeng Phuah, HyoungMin Kim, Myeong Jun Song, Ahn Choi, Daeho Kim, SooYoung Kim, Eun-Bong Kim, David Wang, Shinhaeng Kang, Yuhwan Ro, Seungwoo Seo, JoonHo Song, Jaeyoun Youn, Kyomin Sohn and Nam Sung Kim. "A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications". 2021 IEEE International Solid- State Circuits Conference (ISSCC). February 2021.
Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi,"PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture," ISCA, 2015.
Christina Giannoula, Nandita Vijaykumar, Nikela Papadopoulou, Vasileios Karakostas, Ivan Fernandez, Juan Gómez-Luna, Lois Orosa, Nectarios Koziris, Georgios Goumas, and Onur Mutlu, "SynCron: Efficient Synchronization Support for Near-DataProcessing Architectures". Proceedings of the 27th International Symposium on High-Performance Computer Architecture (HPCA), Virtual, February-March 2021.
Kevin Hsieh, Eiman Ebrahimi, Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Nandita Vijaykumar, Onur Mutlu, and Stephen W. Keckler, "Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems," ISCA, 2016.
Geraldo F. Oliveira, Juan Gómez-Luna, Lois Orosa, Saugata Ghose, Nandita Vijaykumar, Ivan Fernandez, Mohammad Sadrosadati, Onur Mutlu. "DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks".
V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M.A. Kozuch, O. Mutlu, P.B. Gibbons, T.C. Mowry, “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” MICRO, 2017.
V. Seshadri and O. Mutlu, "In-DRAM Bulk Bitwise Execution Engine," Invited Book Chapter in Advances in Computers, to appear in 2020.
Nastaran Hajinazar, Geraldo F. Oliveira, Sven Gregorio, Joao Dinis Ferreira, Nika Mansouri Ghiasi, Minesh Patel, Mohammed Alser, Saugata Ghose, Juan Gomez-Luna, and Onur Mutlu, "SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM". Proceedings of the 26th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Virtual, March-April 2021.
V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, M.A. Kozuch, P.B. Gibbons, T.C. Mowry, "RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization," MICRO, 2013.
K. K. Chang, P. J. Nair, S. Ghose, D. Lee, M. K. Qureshi, O. Mutlu, "Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM," HPCA 2016
Y. Wang, L. Orosa, X. Peng, Y. Guo, S. Ghose, M. Patel, J. S. Kim, J. G. Luna, M. Sadrosadati, N. M. Ghiasi, and O. Mutlu, "FIGARO: Improving System Performance via Fine-Grained In- DRAM Data Relocation and Caching", MICRO 2020
S. H. S. Rezaei, M. Modarressi, R. Ausavarungnirun, M. Sadrosadati, O. Mutlu, and M. Daneshtalab, "NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories", CAL 2020
Jeremie S. Kim, Minesh Patel, Hasan Hassan, and Onur Mutlu, "The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern DRAM Devices". Proceedings of the 24th International Symposium on High-Performance Computer Architecture (HPCA), Vienna, Austria, February 2018.
Jeremie S. Kim, Minesh Patel, Hasan Hassan, Lois Orosa, and Onur Mutlu, "D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput". Proceedings of the 25th International Symposium on High-Performance Computer Architecture (HPCA), Washington, DC, USA, February 2019.
Onur Mutlu, Saugata Ghose, Juan Gomez-Luna, and Rachata Ausavarungnirun, "A Modern Primer on Processing in Memory". Invited Book Chapter in Emerging Computing: From Devices to Systems Looking Beyond Moore and Von Neumann, Springer, to be published in 2021.
S. Ghose, A. Boroumand, J. S. Kim, J. Gomez-Luna, and O. Mutlu, "Processing-in-Memory: A Workload-Driven Perspective," IBM Journal of Research & Development, 2019
Onur Mutlu, "Memory-Centric Computing Systems" Invited Tutorial at 66th International Electron Devices Meeting (IEDM), Virtual, 12 December 2020.
Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu, ”Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors”, ISCA, 2014
Daniel Gruss, Clementine Maurice, and Stefan Mangard, “Rowhammer.js: A Remote Software-Induced Fault Attack in JavaScript” DIMVA 2016
Victor van der Veen, Yanick Fratantonio, Martina Lindorfer, Daniel Gruss, Clémentine Maurice, Giovanni Vigna, Herbert Bos, Kaveh Razavi, and Cristiano Giuffrida, “Drammer: Deterministic Rowhammer Attacks on Mobile Platforms ” CCS 2016
Pietro Frigo, Cristiano Giuffrida, Herbert Bos, Kaveh Razavi, “Grand Pwning Unit: Accelerating Microarchitectural Attacks with the GPU ” S&P 2018
Andrei Tatar, Radhesh Krishnan Konoth, Elias Athanasopoulos, “Throwhammer: Rowhammer Attacks over the Network and Defenses” USENIX ATC 2018
Moritz Lipp, Misiker Tadesse Aga, Michael Schwarz, Daniel Gruss, Clémentine Maurice, Lukas Raab, “Nethammer: Inducing Rowhammer Faults through Network Requests” arXiv 2018
Andrew Kwong, Daniel Genkin, Daniel Gruss, and Yuval Yarom, “RAMBleed: Reading Bits in Memory Without Accessing Them” S&P 2020
Sanghyun Hong, Pietro Frigo, Yiğitcan Kaya, Cristiano Giuffrida, Tudor Dumitraş. "Terminal Brain Damage: Exposing the Graceless Degradation in Deep Neural Networks Under Hardware Fault Attacks". USENIX Security 2019.
Fan Yao, Adnan Siraj Rakin, Deliang Fan. "DeepHammer: Depleting the Intelligence of Deep Neural Networks through Targeted Chain of Bit Flips". USENIX Security 2020.
Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu, ”Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors”, ISCA, 2014
O. Mutlu, J. S. Kim, RowHammer: A Retrospective," arXiv, 2019
Jeremie S. Kim, Minesh Patel, A. Giray Yaglikci, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu, “Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques”, ISCA 2020
Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi, “TRRespass: Exploiting the Many Sides of Target Row Refresh”, S&P 2020
Lucian Cojocar, Jeremie Kim, Minesh Patel, Lillian Tsai, Stefan Saroiu, Alec Wolman, and Onur Mutlu, "Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers," S&P 2020.
A. Giray Yaglikci, Minesh Patel, Jeremie S. Kim, Roknoddin Azizi, Ataberk Olgun, Lois Orosa, Hasan Hassan, Jisung Park, Konstantinos Kanellopoulos, Taha Shahroodi, Saugata Ghose, and Onur Mutlu, "BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows". Proceedings of the 27th International Symposium on High-Performance Computer Architecture (HPCA), Virtual, February-March 2021.
Onur Mutlu, "The Story of RowHammer" Keynote Talk at Secure Hardware, Architectures, and Operating Systems Workshop (SeHAS), held with HiPEAC 2021 Conference, Virtual, 19 January 2021.
Video (1 hour 15 minutes, with Q&A)
Lois Orosa, Abdullah Giray Yaglikci, Haocong Luo, Ataberk Olgun, Jisung Park, Hasan Hassan, Minesh Patel, Jeremie S. Kim, Onur Mutlu, "A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses". MICRO 2021
Hasan Hassan, Yahya Can Tugrul, Jeremie S. Kim, Victor van der Veen, Kaveh Razavi, Onur Mutlu. "Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications". MICRO 2021
D. Senol Cali, J.S. Kim, S. Ghose, C. Alkan, and O. Mutlu, “Nanopore Sequencing Technology and Tools for Genome Assembly: Computational Analysis of the Current State, Bottlenecks and Future Directions,” Briefings in Bioinformatics, 2018
Ebrahim Afshinnekoo, Cem Meydan, Shanin Chowdhury, Dyala Jaroudi, Collin Boyer, Nick Bernstein, Julia M. Maritz, Darryl Reeves, Jorge Gandara, Sagar Chhangawala, Sofia Ahsanuddin, Amber Simmons, Timothy Nessel, Bharathi Sundaresh, Elizabeth Pereira, Ellen Jorgensen, Sergios-Orestis Kolokotronis, Nell Kirchberger, Isaac Garcia, David Gandara, Sean Dhanraj, Tanzina Nawrin, Yogesh Saletore, Noah Alexander, Priyanka Vijay, Elizabeth M. Hénaff, Paul Zumbo, Michael Walsh, Gregory D. O’Mullan, Scott Tighe, Joel T. Dudley, Anya Dunaif, Sean Ennis, Eoghan O’Halloran, Tiago R. Magalhaes, Braden Boone, Angela L. Jones, Theodore R. Muth, Katie Schneider Paolantonio, Elizabeth Alter, Eric E. Schadt, Jeanne Garbarino, Robert J. Prill, Jane M. Carlton, Shawn Levy, and Christopher E. Mason, "Geospatial Resolution of Human and Bacterial Diversity with City-Scale Metagenomics," Cell Systems vol. 1, no. 1 pp. 72–87 Jul. 2015.
Joshua Quick, Nicholas J. Loman, Sophie Duraffour, Jared T. Simpson, Ettore Severi, Lauren Cowley, Joseph Akoi Bore, Raymond Koundouno, Gytis Dudas, Amy Mikhail, Nobila Ouédraogo, Babak Afrough, Amadou Bah, Jonathan H. J. Baum, Beate Becker-Ziaja, Jan Peter Boettcher, Mar Cabeza-Cabrerizo, Álvaro Camino-Sánchez, Lisa L. Carter, Juliane Doerrbecker, Theresa Enkirch, Isabel García- Dorival, Nicole Hetzelt, Julia Hinzmann, Tobias Holm, Liana Eleni Kafetzopoulou, Michel Koropogui, Abigael Kosgey, Eeva Kuisma, Christopher H. Logue, Antonio Mazzarelli, Sarah Meisel, Marc Mertens, Janine Michel, Didier Ngabo, Katja Nitzsche, Elisa Pallasch, Livia Victoria Patrono, Jasmine Portmann, Johanna Gabriella Repits, Natasha Y. Rickett, Andreas Sachse, Katrin Singethan, Inês Vitoriano, Rahel L. Yemanaberhan, Elsa G. Zekeng, Trina Racine, Alexander Bello, Amadou Alpha Sall, Ousmane Faye, Oumar Faye, N’Faly Magassouba, Cecelia V. Williams, Victoria Amburgey, Linda Winona, Emily Davis, Jon Gerlach, Frank Washington, Vanessa Monteil, Marine Jourdain, Marion Bererd, Alimou Camara, Hermann Somlare, Abdoulaye Camara, Marianne Gerard, Guillaume Bado, Bernard Baillet, Déborah Delaune, Koumpingnin Yacouba Nebie, Abdoulaye Diarra, Yacouba Savane, Raymond Bernard Pallawo, Giovanna Jaramillo Gutierrez, Natacha Milhano, Isabelle Roger, Christopher J. Williams, Facinet Yattara, Kuiama Lewandowski, James Taylor, Phillip Rachwal, Daniel J. Turner, Georgios Pollakis, Julian A. Hiscox, David A. Matthews, Matthew K. O’ Shea, Andrew McD. Johnston, Duncan Wilson, Emma Hutley, Erasmus Smit, Antonino Di Caro, Roman Wölfel, Kilian Stoecker, Erna Fleischmann, Martin Gabriel, Simon A. Weller, Lamine Koivogui, Boubacar Diallo, Sakoba Keïta, Andrew Rambaut, Pierre Formenty, Stephan Günther, and Miles W. Carroll, "Real-time, portable genome sequencing for Ebola surveillance," Nature vol. 530, no. 7589 pp. 228–232 Feb. 2016.
H. Xin, D. Lee, F. Hormozdiari, S. Yedkar, O. Mutlu, and C, Alkan, "Accelerating read mapping with FastHASH," BMC Genomics, 2013
Source Code
H. Xin, J. Greth, J. Emmons, G. Pekhimenko, C. Kingsford, C. Alkan, and O. Mutlu, "Shifted Hamming Distance: A Fast and Accurate SIMD-friendly Filter to Accelerate Alignment Verification in Read Mapping,” Bioinformatics, 2015
Source Code
M. Alser, H. Hassan, H. Xin, O. Ergin, O. Mutlu, C. Alkan, "GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping,” Bioinformatics, 2017
J.S. Kim, D. Senol Cali, H. Xin, D. Lee, S. Ghose, M. Alser, H. Hassan, O. Ergin, C. Alkan, and O. Mutlu, "GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies," BMC Genomics, 2018
Mohammed Alser, Hasan Hassan, Akash Kumar, Onur Mutlu, Can Alkan, and Inanc Birol, "Shouji: A fast and efficient pre-alignment filter for sequence alignment," Bioinformatics 2019.
Mohammed Alser, Taha Shahroodi, Juan Gomez-Luna, Can Alkan, and Onur Mutlu, "SneakySnake: A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs," arXiv 2020 https://arxiv.org/pdf/1910.09020.pdf.
Thomas Kuhn. "The Structure of Scientific Revolutions".
J. Liu, B. Jaiyen, R. Veras, O. Mutlu, "RAIDR: Retention-Aware Intelligent DRAM Refresh," ISCA 2012
Mentioned Code Repositories (Lecture 1)
GitHub: SAFARI Research Group
Rowhammer – Program to Induce RowHammer Errors
Ramulator – Fast and Extensible DRAM Simulator
MemSim – Simple Memory Simulator
NOCulator – Flexible Network-on-Chip Simulator
SoftMC – FPGA-Based DRAM Testing Infrastructure
MQSim – A Fast Modern SSD Simulator
Mosaic – GPU Simulator Supporting Concurrent Applications
IMPICA – Processing in 3D-Stacked Memory Simulator
SMLA – Detailed 3D-Stacked Memory Simulator
HWASim – Simulator for Heterogeneous CPU-HWA Systems
Lecture 2 (01.10 Fri.)
Required (Lecture 2)
R.W. Hamming, "You and Your Research", Transcription of the Bell Communications Research Colloquium Seminar, 1986
YouTube: Video Recording of Richard Hamming delivering the talk "You and Your Research" (June 6, 1995)
Mentioned (lecture 2):
Y. Kim, R. Daly, J. Kim, C. Fallin, J.H. Lee, D. Lee, C. Wilkerson, K. Lai, O. Mutlu, "Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors," ISCA 2014
Daniel Gruss, Clementine Maurice, and Stefan Mangard, “Rowhammer.js: A Remote Software-Induced Fault Attack in JavaScript” DIMVA 2016
Victor van der Veen, Yanick Fratantonio, Martina Lindorfer, Daniel Gruss, Clémentine Maurice, Giovanni Vigna, Herbert Bos, Kaveh Razavi, and Cristiano Giuffrida, “Drammer: Deterministic Rowhammer Attacks on Mobile Platforms ” CCS 2016
Pietro Frigo, Cristiano Giuffrida, Herbert Bos, Kaveh Razavi, “Grand Pwning Unit: Accelerating Microarchitectural Attacks with the GPU ” S&P 2018
Andrei Tatar, Radhesh Krishnan Konoth, Elias Athanasopoulos, “Throwhammer: Rowhammer Attacks over the Network and Defenses” USENIX ATC 2018
Moritz Lipp, Misiker Tadesse Aga, Michael Schwarz, Daniel Gruss, Clémentine Maurice, Lukas Raab, “Nethammer:Inducing Rowhammer Faults through Network Requests” arXiv 2018
Andrew Kwong, Daniel Genkin, Daniel Gruss, and Yuval Yarom, “RAMBleed: Reading Bits in Memory Without Accessing Them” S&P 2020
O. Mutlu, J. S. Kim, RowHammer: A Retrospective," arXiv, 2019
Jeremie S. Kim, Minesh Patel, A. Giray Yaglikci, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu, “Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques”, ISCA 2020
Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi, “TRRespass: Exploiting the Many Sides of Target Row Refresh”, S&P 2020
Lucian Cojocar, Jeremie Kim, Minesh Patel, Lillian Tsai, Stefan Saroiu, Alec Wolman, and Onur Mutlu, "Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers", S&P 2020
A. Giray Yaglikci, Minesh Patel, Jeremie S. Kim, Roknoddin Azizi, Ataberk Olgun, Lois Orosa, Hasan Hassan, Jisung Park, Konstantinos Kanellopoulos, Taha Shahroodi, Saugata Ghose, and Onur Mutlu, "BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows". Proceedings of the 27th International Symposium on High-Performance Computer Architecture (HPCA), Virtual, February-March 2021.
Lois Orosa, Abdullah Giray Yaglikci, Haocong Luo, Ataberk Olgun, Jisung Park, Hasan Hassan, Minesh Patel, Jeremie S. Kim, Onur Mutlu, "A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses". MICRO 2021
Hasan Hassan, Yahya Can Tugrul, Jeremie S. Kim, Victor van der Veen, Kaveh Razavi, Onur Mutlu. "Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications". MICRO 2021
Hongyi Xin, John Greth, John Emmons, Gennady Pekhimenko, Carl Kingsford, Can Alkan, and Onur Mutlu, "Shifted Hamming distance: a fast and accurate SIMD-friendly filter to accelerate alignment verification in read mapping," Bioinformatics vol. 31, no. 10 pp. 1553–1560 May 2015.
C. Alkan, J.M. Kidd, T. Marques-Bonet, G. Aksay, F. Antonacci, F. Hormozdiari, J.O. Kitzman, C. Baker, M. Malig, O. Mutlu, S.C. Sahinalp, R.A. Gibbs, E.E. Eichler, "Personalized copy number and segmental duplication maps using next-generation sequencing”, Nature Genetics, 2009
H. Xin, D. Lee, F. Hormozdiari, S. Yedkar, O. Mutlu, and C, Alkan, "Accelerating read mapping with FastHASH," BMC Genomics, 2013
H. Xin, J. Greth, J. Emmons, G. Pekhimenko, C. Kingsford, C. Alkan, and O. Mutlu, "Shifted Hamming Distance: A Fast and Accurate SIMD-friendly Filter to Accelerate Alignment Verification in Read Mapping,” Bioinformatics, 2015
M. Alser, H. Hassan, H. Xin, O. Ergin, O. Mutlu, C. Alkan, "GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping,” Bioinformatics, 2017
M. Alser, O. Mutlu, and C. Alkan, "MAGNET: Understanding and Improving the Accuracy of Genome Pre-Alignment Filtering," IPSI Transactions on Internet Research, 2017
M. Alser, H. Hassan, A. Kumar, O. Mutlu, C. Alkan, "Shouji: A Fast and Efficient Pre-alignment Filter for Sequence Alignment," Bioinformatics, 2019
J.S. Kim, D. Senol Cali, H. Xin, D. Lee, S. Ghose, M. Alser, H. Hassan, O. Ergin, C. Alkan, and O. Mutlu, "GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies," BMC Genomics, 2018
D. Senol Cali, J.S. Kim, S. Ghose, C. Alkan, and O. Mutlu, “Nanopore Sequencing Technology and Tools for Genome Assembly: Computational Analysis of the Current State, Bottlenecks and Future Directions,” Briefings in Bioinformatics, 2018
Damla Senol Cali, Gurpreet S. Kalsi, Zulal Bingol, Can Firtina, Lavanya Subramanian, Jeremie S. Kim, Rachata Ausavarungnirun, Mohammed Alser, Juan Gomez-Luna, Amirali Boroumand, Anant Nori, Allison Scibisz, Sreenivas Subramoney, Can Alkan, Saugata Ghose, and Onur Mutlu, "GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis," MICRO, 2020
Mohammed Alser, Zulal Bingol, Damla Senol Cali, Jeremie Kim, Saugata Ghose, Can Alkan, and Onur Mutlu, "Accelerating Genome Analysis: A Primer on an Ongoing Journey," IEEE Micro 2020.
A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan, and O. Mutlu, "Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,” ASPLOS, 2018.
Lecture 3a (07.10 Thu.)
Described in detail during Lecture 3a:
R. Sites, "It’s the Memory, Stupid!," Microprocessor report 1996
S. Kanev, J. P. Darago, K. M. Hazelwood, P. Ranganathan, T. Moseley, G. Wei, D. M. Brooks, "Profiling a Warehouse-scale Computer," ISCA, 2015.
O. Mutlu, J. Stark, C. Wilkerson, Y.N. Patt, "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors," HPCA 2003
Suggested (Lecture 3a):
H. Xin, D. Lee, F. Hormozdiari, S. Yedkar, O. Mutlu, and C, Alkan, "Accelerating read mapping with FastHASH," BMC Genomics, 2013
H. Xin, J. Greth, J. Emmons, G. Pekhimenko, C. Kingsford, C. Alkan, and O. Mutlu, "Shifted Hamming Distance: A Fast and Accurate SIMD-friendly Filter to Accelerate Alignment Verification in Read Mapping,” Bioinformatics, 2015
M. Alser, H. Hassan, H. Xin, O. Ergin, O. Mutlu, C. Alkan, "GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping,” Bioinformatics, 2017
M. Alser, O. Mutlu, and C. Alkan, "MAGNET: Understanding and Improving the Accuracy of Genome Pre-Alignment Filtering," IPSI Transactions on Internet Research, 2017
M. Alser, H. Hassan, A. Kumar, O. Mutlu, and C. Alkan, "SLIDER: Fast and Efficient Computation of Banded Sequence Alignment," arXiv 2018
J.S. Kim, D. Senol Cali, H. Xin, D. Lee, S. Ghose, M. Alser, H. Hassan, O. Ergin, C. Alkan, and O. Mutlu, "GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies," to appear in BMC Genomics, 2018
D. Senol Cali, J.S. Kim, S. Ghose, C. Alkan, and O. Mutlu, “Nanopore Sequencing Technology and Tools for Genome Assembly: Computational Analysis of the Current State, Bottlenecks and Future Directions,” to appear in Briefings in Bioinformatics, 2018
S. Wang, E. Ipek. "Reducing Data Movement Energy via Online data Clustering and Encoding,” MICRO, 2016.
D. Pandiyan, and C. Wu. "Quantifying the Energy Cost of Data Movement for Emerging Smart Phone Workloads on Mobile Platforms." IISWC, 2014.
K. Lim, J. Chang, T. Mudge, P. Ranganathan, S.K. Reinhardt, T.F. Wenisch, "Disaggregated Memory for Expansion and Sharing in Blade Servers," ISCA 2009
C. Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler, T.W. Keller, "Energy Management for Commercial Servers", IEEE Computer, 2003
S. Rixner, W.J. Dally, U.J. Kapasi, P. Mattson, J.D. Owens, "Memory access scheduling," ISCA 2000
A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan, and O. Mutlu, "Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,” ASPLOS, 2018.
J. Meza, Q. Wu, S. Kumar, O. Mutlu, "Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field," DSN 2015
Hasan Hassan, Nandita Vijaykumar, Samira Khan, Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, and Onur Mutlu, "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies," HPCA 2017
Y. Kim, R. Daly, J. Kim, C. Fallin, J.H. Lee, D. Lee, C. Wilkerson, K. Lai, O. Mutlu, "Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors," ISCA 2014
O. Mutlu, J. S. Kim, RowHammer: A Retrospective," arXiv, 2019
J. Meza, J. Chang, H. Yoon, O. Mutlu, and P. Ranganathan, "Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management" CAL 2012
H. Yoon, J. Meza, R. Ausavarungnirun, R. Harding, and O. Mutlu, "Row Buffer Locality Aware Caching Policies for Hybrid Memories" ICCD 2012
U. Kang, H.-S. Yu, C. Park, H. Zheng, J. Halbert, K. Bains, S. Jang, J.S. Choi, "Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling," The Memory Forum 2014
Lecture 3c (07.10 Thu.)
Described in detail during Lecture 3c:
T. Moscibroda and O. Mutlu. "Memory performance attacks: denial of memory service in multi-core systems," USENIX Security Symposium 2007
Suggested (Lecture 3c):
Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter Mattson, and John D. Owens, “Memory Access Scheduling”, ISCA, 2000
Zuravleff and Robinson. "Controller for a synchronous DRAM the maximizes throughput by allowing memory requests and commands to be issued out of order," US Patent 5,630,096, 1997
Onur Mutlu Thomas Moscibroda, “Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors”, MICRO, 2007
Onur Mutlu Thomas Moscibroda, “Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems”, ISCA, 2008
Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, Thomas Moscibroda, “Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning”, MICRO, 2011
Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, Onur Mutlu, “The Blacklisting Memory Scheduler: Achieving High Performance and Fairness at Low Cost”, ICCD, 2014
Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, and Onur Mutlu, ”BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling”, TPDS, 2016
Boris Grot, Stephen W. Keckler, Onur Mutlu, “Preemptive Virtual Clock: A Flexible, Efficient, and Cost-effective QOS Scheme for Networks-on-Chip”, MICRO, 2009
Lecture 4a (08.10 Fri.)
Described in detail during Lecture 4a:
T. Moscibroda and O. Mutlu. "Memory performance attacks: denial of memory service in multi-core systems," USENIX Security Symposium 2007
Suggested (Lecture 4a):
Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, Thomas Moscibroda, “Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning”, MICRO, 2011
Boris Grot, Stephen W. Keckler, Onur Mutlu, “Preemptive Virtual Clock: A Flexible, Efficient, and Cost-effective QOS Scheme for Networks-on-Chip”, MICRO, 2009
Lecture 4b (08.10 Fri.)
Described in detail during Lecture 4b:
J. Liu, B. Jaiyen, R. Veras, O. Mutlu, "RAIDR: Retention-Aware Intelligent DRAM Refresh," ISCA 2012
Suggested (Lecture 4b):
Samira Khan, Donghyuk Lee, Yoongu Kim, Alaa Alameldeen, Chris Wilkerson, and Onur Mutlu, "The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study", SIGMETRICS 2014
J. Liu, B. Jaiyen, Y. Kim, C, Wilkerson and O. Mutlu, "An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms", ISCA 2013
Moinuddin Qureshi, Dae Hyun Kim, Samira Khan, Prashant Nair, and Onur Mutlu, "AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems", DSN 2015
Kevin Chang, Donghyuk Lee, Zeshan Chishti, Alaa Alameldeen, Chris Wilkerson, Yoongu Kim, and Onur Mutlu, "Improving DRAM Performance by Parallelizing Refreshes with Accesses", HPCA 2014
Samira Khan, Donghyuk Lee, and Onur Mutlu, "PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM", DSN 2016
Samira Khan, Chris Wilkerson, Zhe Wang, Alaa R. Alameldeen, Donghyuk Lee, and Onur Mutlu, "Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content", MICRO 2017
Minesh Patel, Jeremie S. Kim, and Onur Mutlu, "Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content", ISCA 2017
Minesh Patel, Jeremie S. Kim, Hasan Hassan, and Onur Mutlu, "Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices", DSN 2019
Minesh Patel, Jeremie S. Kim, Taha Shahroodi, Hasan Hassan, and Onur Mutlu, "Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics", MICRO 2020
Vivek Seshadri, Onur Mutlu, Michael A. Kozuch, and Todd C. Mowry, "The Evicted-Address Filter: A Unified Mechanism to Address Both Cache Pollution and Thrashing", PACT 2021
Minesh Patel, Geraldo F. Oliveira and Onur Mutlu, "HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes", MICRO 2021
Lecture 5 (14.10 Thu.)
Described in detail during Lecture 5:
Onur Mutlu and Jeremie Kim, "RowHammer: A Retrospective", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) Special Issue on Top Picks in Hardware and Embedded Security, 2019.
Sudhakar Govindavajhala, Andrew W. Appel, "Using Memory Errors to Attack a Virtual Machine", 2003 Symposium on Security and Privacy, 2003.IEEE, 2003
Frigo, Pietro, Emanuele Vannacc, Hasan Hassan, Victor Van Der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi. "TRRespass: Exploiting the many sides of target row refresh." In 2020 IEEE Symposium on Security and Privacy (SP), pp. 747-762. IEEE, 2020.
Suggested (Lecture 5):
Justin Meza, Qiang Wu, Sanjeev Kumar, and Onur Mutlu, "Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field", DSN 2015
Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, and Onur Mutlu, "Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors", ISCA 2014
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Khan, Vivek Seshadri, Kevin Chang, and Onur Mutlu, "Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case", HPCA 2015
Moinuddin Qureshi, Dae Hyun Kim, Samira Khan, Prashant Nair, and Onur Mutlu, "AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems", DSN 2015
Hasan Hassan, Nandita Vijaykumar, Samira Khan, Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, and Onur Mutlu, "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies", HPCA 2017
J. Liu, B. Jaiyen, R. Veras, O. Mutlu, "RAIDR: Retention-Aware Intelligent DRAM Refresh", ISCA 2012
Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, and Onur Mutlu, "An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms", ISCA 2013
Samira Khan, Donghyuk Lee, Yoongu Kim, Alaa Alameldeen, Chris Wilkerson, and Onur Mutlu, "The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study", SIGMETRICS 2014
Minesh Patel, Jeremie S. Kim, and Onur Mutlu, "The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions", ISCA 2017
Minesh Patel, Jeremie S. Kim, Hasan Hassan, and Onur Mutlu, "Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices", DSN 2019
Minesh Patel, Jeremie S. Kim, Taha Shahroodi, Hasan Hassan, and Onur Mutlu, "Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics", MICRO 2020
Sudhakar Govindavajhala, Andrew W. Appel, "Using Memory Errors to Attack a Virtual Machine", 2003 Symposium on Security and Privacy, 2003.IEEE, 2003
O. Mutlu, J. S. Kim, "RowHammer: A Retrospective", arXiv 2019
Jeremie S. Kim, Minesh Patel, A. Giray Yaglikci, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu, "Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques", ISCA 2020
Yuan Xiao, Xiaokuan Zhang, Yinqian Zhang, and Radu Teodorescu, "One bit flips, one cloud flops: cross-VM row hammer attacks and privilege escalation", USENIX SEC 2016
Van Der Veen, Victor, Yanick Fratantonio, Martina Lindorfer, Daniel Gruss, Clémentine Maurice, Giovanni Vigna, Herbert Bos, Kaveh Razavi, and Cristiano Giuffrida, "Drammer: Deterministic Rowhammer Attacks on Mobile Platforms", Proceedings of the 2016 ACM SIGSAC conference on computer and communications security, pp. 1675-1689. 2016
Frigo, Pietro, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi. , "Grand pwning unit: Accelerating microarchitectural attacks with the GPU.", In 2018 ieee symposium on security and privacy (sp), pp. 195-210. IEEE, 2018
Tatar, Andrei, Radhesh Krishnan Konoth, Elias Athanasopoulos, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi, "Throwhammer: Rowhammer attacks over the network and defenses.", USENIX ATC, 2018
Kwong, Andrew, Daniel Genkin, Daniel Gruss, and Yuval Yarom., "Rambleed: Reading bits in memory without accessing them.", In 2020 IEEE Symposium on Security and Privacy (SP), pp. 695-711. IEEE, 2020
Hong, Sanghyun, Pietro Frigo, Yiğitcan Kaya, Cristiano Giuffrida, and Tudor Dumitraș. "Terminal brain damage: Exposing the graceless degradation in deep neural networks under hardware fault attacks." In 28th {USENIX} Security Symposium ({USENIX} Security 19), pp. 497-514. 2019.
Yao, Fan, Adnan Siraj Rakin, and Deliang Fan. "Deephammer: Depleting the intelligence of deep neural networks through targeted chain of bit flips." In 29th {USENIX} Security Symposium ({USENIX} Security 20), pp. 1463-1480. 2020.
Kang, Uksong, Hak-Soo Yu, Churoo Park, Hongzhong Zheng, John Halbert, Kuljit Bains, S. Jang, and Joo Sun Choi. "Co-architecting controllers and DRAM to enhance DRAM process scaling." In The memory forum, vol. 14. 2014.
Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, and Onur Mutlu,"Error Characterization, Mitigation, and Recovery in Flash Memory Based Solid State Drives"Proceedings of the IEEE, 2017
Onur Mutlu,"The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser", Invited Paper in Proceedings of the Design, Automation, and Test in Europe Conference (DATE), Lausanne, Switzerland, March 2017
Frigo, Pietro, Emanuele Vannacc, Hasan Hassan, Victor Van Der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi. "TRRespass: Exploiting the many sides of target row refresh." In 2020 IEEE Symposium on Security and Privacy (SP), pp. 747-762. IEEE, 2020.
Lucian Cojocar, Jeremie Kim, Minesh Patel, Lillian Tsai, Stefan Saroiu, Alec Wolman, and Onur Mutlu,"Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers", Proceedings of the 41st IEEE Symposium on Security and Privacy (S&P), San Francisco, CA, USA, May 2020
A. Giray Yaglikci, Minesh Patel, Jeremie S. Kim, Roknoddin Azizi, Ataberk Olgun, Lois Orosa, Hasan Hassan, Jisung Park, Konstantinos Kanellopoulos, Taha Shahroodi, Saugata Ghose, and Onur Mutlu,""BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows"", HPCA 2021
Son, Mungyu, Hyunsun Park, Junwhan Ahn, and Sungjoo Yoo. "Making DRAM stronger against row hammering." DAC 2017
You, Jung Min, and Joon-Sung Yang. "MRLoc: Mitigating Row-hammering based on memory Locality." In 2019 56th ACM/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE, 2019.
Lee, Eojin, Ingab Kang, Sukhan Lee, G. Edward Suh, and Jung Ho Ahn. "TWiCe: preventing row-hammering by exploiting time window counters." In Proceedings of the 46th International Symposium on Computer Architecture, pp. 385-396. 2019.
Lecture 6a (15.10 Thu.)
Described in detail during Lecture 6a:
Suggested (Lecture 6a):
Justin Meza, Qiang Wu, Sanjeev Kumar, and Onur Mutlu, "Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field", DSN 2015
Justin Meza, Qiang Wu, Sanjeev Kumar, and Onur Mutlu, "A Large-Scale Study of Flash Memory Errors in the Field", SIGMETRICS 2015
Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, and Onur Mutlu, "An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms", ISCA 2013
Uksong Kang, Hak-soo Yu, Churoo Park, Hongzhong Zheng, John Halbert, Kuljit Bains, SeongJin Jang, and Joo Sun Choi, "Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling," The Memory Forum 2014
Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, and Onur Mutlu, "Error Characterization, Mitigation, and Recovery in Flash Memory Based Solid-State Drives," Proc. IEEE 2017
Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, and Onur Mutlu, Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu, ”Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors”, ISCA, 2014
Yu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch, ”Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques”, HPCA, 2017
Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu, ”HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness”, HPCA, 2018
Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu, ”Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation”, SIGMETRICS, 2018
Leslie Lamport, Robert Shostak, and Marshall Pease, ”The Byzantine Generals Problem”, TOPLAS, 1982
Onur Mutlu and Jeremie Kim, "RowHammer: A Retrospective", (TCAD) Special Issue on Top Picks in Hardware and Embedded Security, 2019
Jeremie S. Kim, Minesh Patel, A. Giray Yaglikci, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu, "Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques", ISCA 2020
Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi, "TRRespass: Exploiting the Many Sides of Target Row Refresh", S&P, 2020
Lucian Cojocar, Jeremie Kim, Minesh Patel, Lillian Tsai, Stefan Saroiu, Alec Wolman, and Onur Mutlu, "Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers", S&P, 2020
A.Giray Yaglikci, Minesh Patel, Jeremie S.Kim, Roknoddin Azizi, Ataberk Olgun, Lois Orosa, Hasan Hassan, Jisung Park, Konstantinos Kanellopoulos, Taha Shahroodi, Saugata Ghose, and Onur Mutlu, "BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows", HPCA, 2021
Lois Orosa, Abdullah Giray Yaglikci, Haocong Luo, Ataberk Olgun, Jisung Park, Hasan Hassan, Minesh Patel, Jeremie S. Kim, Onur Mutlu,"A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses" to appear in MICRO 2021
Hasan Hassan, Yahya Can Tugrul, Jeremie S. Kim, Victor van der Veen, Kaveh Razavi, Onur Mutlu, "Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications" to appear in MICRO 2021
Lecture 6b (15.10 Thu.)
Described in detail during Lecture 6a:
V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, M.A. Kozuch, P.B. Gibbons, T.C. Mowry, "RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization," MICRO, 2013
K. K. Chang, P. J. Nair, S. Ghose, D. Lee, M. K. Qureshi, O. Mutlu, "Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM," HPCA 2016
Suggested (Lecture 6b):
Burks, Goldstein, von Neumann, “Preliminary discussion of the logical design of an electronic computing instrument,” The Origins of Digital Computers, 1946
O. Mutlu, J. Stark, C. Wilkerson, Y.N. Patt, "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors," HPCA 2003
Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt, "Runahead Execution: An Effective Alternative to Large Instruction Windows" IEEE Mircro 2003(MICRO TOP PICKS)
R. Sites, "It’s the Memory, Stupid!," Microprocessor report 1996
Madeleine Gray and Onur Mutlu, "It’s the memory, stupid’: A conversation with Onur Mutlu" HiPEAC Newsletter 2018
S. Kanev, J. P. Darago, K. M. Hazelwood, P. Ranganathan, T. Moseley, G. Wei, D. M. Brooks, "Profiling a Warehouse-scale Computer," ISCA, 2015
A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan, and O. Mutlu, "Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,” ASPLOS, 2018
Onur Mutlu, Saugata Ghose, Juan Gomez-Luna, and Rachata Ausavarungnirun, "A Modern Primer on Processing in Memory”, Invited Book Chapter in Emerging Computing: From Devices to Systems - Looking Beyond Moore and Von Neumann, Springer, to be published in 2021
Kautz, “Cellular Logic-in-Memory Arrays”, IEEE TC 1969
Harold Stone, "A Login-in-Memory Computer" IEEE TC 1970
Onur Mutlu, "Memory Scaling: A Systems Architecture Perspective", IMW 2013
Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, "A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing", ISCA 2015
Juan Gómez-Luna, Izzat El Hajj, Ivan Fernandez, Christina Giannoula, Geraldo F. Oliveira, Onur Mutlu. "Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture".
Gagandeep Singh, Mohammed Alser, Damla Senol Cali, Dionysios Diamantopoulos, Juan Gómez-Luna, Henk Corporaal, and Onur Mutlu, "FPGA-based Near-Memory Acceleration of Modern Data-Intensive Applications" IEEE Micro (IEEE MICRO), to appear, 2021.
V. Seshadri, K. Hsieh, A. Boroumand, D. Lee, M.A. Kozuch, O.Mutlu, P.B. Gibbons, T.C. Mowry, "Fast Bulk Bitwise AND and OR in DRAM," IEEE CAL, 2015
Vivek Seshadri, Thomas Mullins, Amirali Boroumand, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry, "Gather-Scatter DRAM: In-DRAM Address Translation to Improve the Spatial Locality of Non-unit Strided Accesses"
V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M.A. Kozuch, O. Mutlu, P.B. Gibbons, T.C. Mowry, “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” MICRO, 2017.
Y. Wang, L. Orosa, X. Peng, Y. Guo, S. Ghose, M. Patel, J. S. Kim, J. G. Luna, M. Sadrosadati, N. M. Ghiasi, and O. Mutlu, "FIGARO: Improving System Performance via Fine-Grained In- DRAM Data Relocation and Caching", MICRO 2020
S. H. S. Rezaei, M. Modarressi, R. Ausavarungnirun, M. Sadrosadati, O. Mutlu, and M. Daneshtalab, "NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories", CAL 2020
Vivek Seshadri and Onur Mutlu, "In-DRAM Bulk Bitwise Execution Engine," Invited Book Chapter in Advances in Computers, 2020
Nastaran Hajinazar, Geraldo F. Oliveira, Sven Gregorio, Joao Dinis Ferreira, Nika Mansouri Ghiasi, Minesh Patel, Mohammed Alser, Saugata Ghose, Juan Gomez-Luna, and Onur Mutlu, "SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM," ASPLOS 2021
Lecture 7 (21.10 Thu.)
Described in detail during lecture 7:
A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan, and O. Mutlu, "Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,” ASPLOS, 2018.
V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, M.A. Kozuch, P.B. Gibbons, T.C. Mowry, "RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization," MICRO, 2013.
V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M.A. Kozuch, O. Mutlu, P.B. Gibbons, T.C. Mowry, “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” MICRO, 2017.
V. Seshadri, K. Hsieh, A. Boroumand, D. Lee, M.A. Kozuch, O.Mutlu, P.B. Gibbons, T.C. Mowry, "Fast Bulk Bitwise AND and OR in DRAM," IEEE CAL, 2015.
F. Gao, G. Tziantzioulis, D. Wentzlaff, "ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs," MICRO, 2019.
Suggested (lecture 7):
O. Mutlu, J. Stark, C. Wilkerson, Y.N. Patt, "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors," HPCA 2003
K. K. Chang, P. J. Nair, S. Ghose, D. Lee, M. K. Qureshi, O. Mutlu, "Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM," HPCA 2016
Y. Wang, L. Orosa, X. Peng, Y. Guo, S. Ghose, M. Patel, J. S. Kim, J. G. Luna, M. Sadrosadati, N. M. Ghiasi, and O. Mutlu, "FIGARO: Improving System Performance via Fine-Grained In- DRAM Data Relocation and Caching", MICRO 2020
S. H. S. Rezaei, M. Modarressi, R. Ausavarungnirun, M. Sadrosadati, O. Mutlu, and M. Daneshtalab, "NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories", CAL 2020
V. Seshadri and O. Mutlu, "In-DRAM Bulk Bitwise Execution Engine," Invited Book Chapter in Advances in Computers, to appear in 2020.
S. Li, C. Xu, Q. Zou, J. Zhao, Y. Lu, and Y. Xie, "Pinatubo: A Processing-in-Memory Architecture for Bulk Bitwise Operations in Emerging Non-volatile Memories," DAC, 2016
Raj Jain, “The Art of Computer Systems Performance Analysis,” Wiley, 1991.
Lecture 8 (22.10 Fri.)
Described in detail during Lecture 8:
Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, "A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing," ISCA, 2015.
A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan, and O. Mutlu, "Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,” ASPLOS, 2018.
Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi,"PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture," ISCA, 2015.
A. Boroumand, S. Ghose, M. Patel, H. Hassan, B. Lucia, R. Ausavarungnirun, K. Hsieh, N. Hajinazar, K.T. Malladi, H. Zheng, and O. Mutlu, "CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators," ISCA 2019
C. Giannoula, N. Vijaykumar, N. Papadopoulou, V. Karakostas, I. Fernandez, J. Gómez-Luna, L. Orosa, N. Koziris, G. Goumas, and O. Mutlu, "SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures,” HPCA, 2021.
Suggested (Lecture 8):
V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, M.A. Kozuch, P.B. Gibbons, T.C. Mowry, "RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization," MICRO, 2013.
Vivek Seshadri, Kevin Hsieh, Amirali Boroumand, Donghyuk Lee, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, and Todd C. Mowry, "Fast Bulk Bitwise and and or in DRAM," IEEE Computer Architecture Letters 2015.
Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie Kim, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, and Todd C. Mowry, "Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology," MICRO, 2017.
Vivek Seshadri and Onur Mutlu, "In-DRAM Bulk Bitwise Execution Engine," arXiv 2020 https://arxiv.org/abs/1905.09822.
Fei Gao, Georgios Tziantzioulis, and David Wentzlaff, "ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs," MICRO, 2019.
Shuangchen Li, Cong Xu, Qiaosha Zou, Jishen Zhao, Yu Lu, and Yuan Xie, "Pinatubo: A Processing-in-Memory Architecture for Bulk Bitwise Operations in Emerging Non-volatile Memories," in Proceedings of the 53rd Annual Design Automation Conference (DAC), 2016, pp. 1–6.
N. Hajinazar, G. F. Oliveira, S. Gregorio, J. D. Ferreira, N. M. Ghiasi, M. Patel, M. Alser, S. Ghose, J. Gomez-Luna, and O. Mutlu, "SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM," in ASPLOS, 2021.
Kevin Hsieh, Eiman Ebrahimi, Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Nandita Vijaykumar, Onur Mutlu, and Stephen W. Keckler, "Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems," ISCA, 2016.
Ashutosh Pattnaik, Xulong Tang, Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, and Chita R. Das, "Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities," PACT, 2016.
Kevin Hsieh, Samira Khan, Nandita Vijaykumar, Kevin K. Chang, Amirali Boroumand, Saugata Ghose, and Onur Mutlu, "Accelerating Pointer Chasing in 3D-Stacked Memory: Challenges, Mechanisms, Evaluation," ICCD, 2016.
Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt, "Accelerating Dependent Cache Misses with an Enhanced Memory Controller," ISCA, 2016.
Milad Hashemi, Onur Mutlu, and Yale N. Patt, "Continuous Runahead: Transparent Hardware Acceleration for Memory Intensive Workloads," MICRO, 2016.
G. Singh, D. Diamantopoulos, C. Hagleitner, J. Gómez-Luna, S. Stuijk, O. Mutlu, and H. Corporaal, "NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling," FPL, 2020
Damla Senol Cali, Gurpreet S. Kalsi, Zulal Bingol, Can Firtina, Lavanya Subramanian, Jeremie S. Kim, Rachata Ausavarungnirun, Mohammed Alser, Juan Gomez-Luna, Amirali Boroumand, Anant Nori, Allison Scibisz, Sreenivas Subramoney, Can Alkan, Saugata Ghose, and Onur Mutlu, "GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis," MICRO, 2020
I. Fernandez, R. Quislant, C. Giannoula, M. Alser, J. Gómez-Luna, E. Gutiérrez, O. Plata, and O. Mutlu, "NATSA: A Near-Data Processing Accelerator for Time Series Analysis," ICCD, 2020
O. Mutlu, S. Ghose, J. Gomez-Luna, and R. Ausavarungnirun, "A Modern Primer on Processing in Memory", Invited Book Chapter in Emerging Computing: From Devices to Systems - Looking Beyond Moore and Von Neumann, Springer, to be published in 2021.
Saugata Ghose, Amirali Boroumand, Jeremie S. Kim, Juan Gomez-Luna, and Onur Mutlu, "Processing-in-Memory: A Workload-Driven Perspective," IBM Journal of Research & Development, 2019
Z. Liu, I. Calciu, M. Herlihy, and O. Mutlu, "Concurrent Data Structures for Near-Memory Computing," SPAA 2017
G. F. Oliveira, J. Gomez-Luna, L. Orosa, S. Ghose, N. Vijaykumar, I. Fernandez, M. Sadrosadati, and O. Mutlu, "DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks"," IEEE Access, 2021
Hasan Hassan, Nandita Vijaykumar, Samira Khan, Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, Onur Mutlu, ”SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies”HPCA, 2017
Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, Onur Mutlu, “An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms”, ISCA, 2013
Arash Tavakkol, Juan Gomez-Luna, Mohammad Sadrosadati, Saugata Ghose, and Onur Mutlu, "MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices", In USENIX FAST, 2018
J.S. Kim, D. Senol Cali, H. Xin, D. Lee, S. Ghose, M. Alser, H. Hassan, O. Ergin, C. Alkan, and O. Mutlu, "GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies," BMC Genomics, 2018
Lecture 9 (28.10 Thu.)
Described in detail during lecture 9:
Juan Gomez-Luna, Izzat El Hajj, Ivan Fernandez, Christina Giannoula, Geraldo F. Oliveira, and Onur Mutlu, "Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture" Preprint in arXiv, 9 May 2021.
Geraldo F. Oliveira, Juan Gomez-Luna, Lois Orosa, Saugata Ghose, Nandita Vijaykumar, Ivan fernandez, Mohammad Sadrosadati, and Onur Mutlu, "DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks" Preprint in arXiv, 8 May 2021.
Suggested (Lecture 9):
Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Michael A. Kozuch, Phillip B. Gibbons, and Todd C. Mowry, "RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization," in MICRO 2013.
Vivek Seshadri, Kevin Hsieh, Amirali Boroumand, Donghyuk Lee, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, and Todd C. Mowry, "Fast Bulk Bitwise AND and OR in DRAM," in CAL 2015.
Vivek Seshadri et al., “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” in MICRO 2017.
Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Michael A. Kozuch, Phillip B. Gibbons, and Todd C. Mowry, "RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization," in MICRO 2013.
Fei Gao, Georgios Tziantzioulis, David Wentzlaf, "ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs," in MICRO 2019.
Shuangchen Li, Cong Xu, Qiaosha Zou, Jishen Zhao, Yu Lu, and Yuan Xie, "Pinatubo: A Processing-in-Memory Architecture for Bulk Bitwise Operations in Emerging Non-volatile Memories," in DAC 2016.
Nastaran Hajinazar, Geraldo F. Oliveira, Sven Gregorio, Joao Dinis Ferreira, Nika Mansouri Ghiasi, Minesh Patel, Mohammed Alser, Saugata Ghose, Juan Gomez-Luna, and Onur Mutlu, "SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM," in ASPLOS 2021.
Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, "A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing," in ISCA 2015.
Amirali Boroumand, Saugata Ghose, Youngsok Kim, Rachata Ausavarungnirun, Eric Shiu, Rahul Thakur, Daehyun Kim, Aki Kuusela, Allan Knies, Parthasarathy Ranganathan, and Onur Mutlu, "Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks," in ASPLOS 2018.
Kevin Hsieh, Eiman Ebrahimi, Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Nandita Vijaykumar, Onur Mutlu, and Stephen W. Keckler, "Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems," in ISCA 2016.
Ashutosh Pattnaik, Xulong Tang, Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, and Chita R. Das, "Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities," in PACT 2016.
Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, "PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture," in ISCA 2015.
Amirali Boroumand, Saugata Ghose, Minesh Patel, Hasan Hassan, Brandon Lucia, Kevin Hsieh, Krishna T. Malladi, Hongzhong Zheng, and Onur Mutlu, "LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory," in CAL 2016.
Amirali Boroumand, Saugata Ghose, Minesh Patel, Hasan Hassan, Brandon Lucia, Kevin Hsieh, Krishna T. Malladi, Hongzhong Zheng, and Onur Mutlu, "CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators," in ISCA 2019.
Christina Giannoula, Nandita Vijaykumar, Nikela Papadopoulou, Vasileios Karakostas, Ivan Fernandez, Juan Gómez-Luna, Lois Orosa, Nectarios Koziris, Georgios Goumas, Onur Mutlu, "SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures," in HPCA 2021.
Kevin Hsieh, Samira Khan, Nandita Vijaykumar, Kevin K. Chang, Amirali Boroumand, Saugata Ghose, and Onur Mutlu, "Accelerating Pointer Chasing in 3D-Stacked Memory: Challenges, Mechanisms, Evaluation," in ICCD 2016.
Zhiyu Liu, Irina Calciu, Maurice Herlihy, and Onur Mutlu, "Concurrent Data Structures for Near-Memory Computing," in SPAA 2017.
Gagandeep Singh, Juan Gomez-Luna, Giovanni Mariani, Geraldo F. Oliveira, Stefano Corda, Sander Stujik, Onur Mutlu, and Henk Corporaal, "NAPEL: Near-Memory Computing Application Performance Prediction via Ensemble Learning," in DAC 2019.
Lecture 10 (29.10 Fri.)
Described in detail during lecture 10:
C. Alkan, J.M. Kidd, T. Marques-Bonet, G. Aksay, F. Antonacci, F. Hormozdiari, J.O. Kitzman, C. Baker, M. Malig, O. Mutlu, S.C. Sahinalp, R.A. Gibbs, E.E. Eichler, "Personalized copy number and segmental duplication maps using next-generation sequencing”, Nature Genetics, 2009
Mohammed Alser, Zulal Bingol, Damla Senol Cali, Jeremie Kim, Saugata Ghose, Can Alkan, and Onur Mutlu, "Accelerating Genome Analysis: A Primer on an Ongoing Journey," IEEE Micro 2020.
Hongyi Xin, Donghyuk Lee, Farhad Hormozdiari, Samihan Yedkar, Onur Mutlu, and Can Alkan, "Accelerating read mapping with FastHASH," BMC Genomics 2013.
Mohammed Alser, Hasan Hassan, Hongyi Xin, Oguz Ergin, Onur Mutlu, and Can Alkan, "GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping," Bioinformatics 2017.
Mohammed Alser, Hasan Hassan, Akash Kumar, Onur Mutlu, Can Alkan, and Inanc Birol, "Shouji: A fast and efficient pre-alignment filter for sequence alignment," Bioinformatics 2019.
Mohammed Alser, Taha Shahroodi, Juan Gomez-Luna, Can Alkan, and Onur Mutlu, "SneakySnake: A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs," arXiv 2020 https://arxiv.org/pdf/1910.09020.pdf.
Gagandeep Singh, Mohammed Alser, Damla Senol Cali, Dionysios Diamantopoulos, Juan Gomez-Luna, Henk Corporaal, Onur Mutlu, “FPGA-Based Near-Memory Acceleration of Modern Data-Intensive Applications“ IEEE Micro, 2021.
Jeremie S. Kim, Damla Senol Cali, Hongyi Xin, Donghyuk Lee, Saugata Ghose, Mohammed Alser, Hasan Hassan, Oguz Ergin, Can Alkan, and Onur Mutlu, "GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies," BMC Genomics vol. 19, no. S2 p. 89 May 2018.
Anirban Nag, C. N. Ramachandra, Rajeev Balasubramonian, Ryan Stutsman, Edouard Giacomin, Hari Kambalasubramanyam, and Pierre-Emmanuel Gaillardon, "GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment," MICRO, 2019.
Damla Senol Cali, Gurpreet S. Kalsi, Zülal Bingöl, Can Firtina, Lavanya Subramanian, Jeremie S. Kim, Rachata Ausavarungnirun, Mohammed Alser, Juan Gomez-Luna, Amirali Boroumand, Anant Nori, Allison Scibisz, Sreenivas Subramoney, Can Alkan, Saugata Ghose, and Onur Mutlu, "GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis," arXiv 2020 https://arxiv.org/abs/2009.07692.
Jeremie S. Kim, Can Firtina, Damla Senol Cali, Mohammed Alser, Nastaran Hajinazar, Can Alkan, and Onur Mutlu, "AirLift: A Fast and Comprehensive Technique for Translating Alignments between Reference Genomes," arXiv 2019 https://arxiv.org/abs/1912.08735.
Suggested (Lecture 10):
Michael Wainberg, Nasa Sinnott-Armstrong, Nicholas Mancuso, Alvaro N. Barbeira, David A. Knowles, David Golan, Raili Ermel, Arno Ruusalepp, Thomas Quertermous, Ke Hao, Johan L. M. Björkegren, Hae Kyung Im, Bogdan Pasaniuc, Manuel A. Rivas, and Anshul Kundaje, "Opportunities and challenges for transcriptome-wide association studies," Nature Genetics vol. 51, no. 4 pp. 592–599 Apr. 2019.
Lauge Farnaes, Amber Hildreth, Nathaly M. Sweeney, Michelle M. Clark, Shimul Chowdhury, Shareef Nahas, Julie A. Cakici, Wendy Benson, Robert H. Kaplan, Richard Kronick, Matthew N. Bainbridge, Jennifer Friedman, Jeffrey J. Gold, Yan Ding, Narayanan Veeraraghavan, David Dimmock, and Stephen F. Kingsmore, "Rapid whole-genome sequencing decreases infant morbidity and cost of hospitalization," NPJ Genomic Medicine vol. 3, no. 1 p. 10 Dec. 2018.
Eleazar Eskin: Discovering the Causal Variants Involved in GWAS Studies, CGSI 2018, UCLA.
Steve S. Ho, Alexander E. Urban, and Ryan E. Mills, "Structural variation in the sequencing era," Nature Reviews Genetics. 2020.
Joshua Quick, Nicholas J. Loman, Sophie Duraffour, Jared T. Simpson, Ettore Severi, Lauren Cowley, Joseph Akoi Bore, Raymond Koundouno, Gytis Dudas, Amy Mikhail, Nobila Ouédraogo, Babak Afrough, Amadou Bah, Jonathan H. J. Baum, Beate Becker-Ziaja, Jan Peter Boettcher, Mar Cabeza-Cabrerizo, Álvaro Camino-Sánchez, Lisa L. Carter, Juliane Doerrbecker, Theresa Enkirch, Isabel García- Dorival, Nicole Hetzelt, Julia Hinzmann, Tobias Holm, Liana Eleni Kafetzopoulou, Michel Koropogui, Abigael Kosgey, Eeva Kuisma, Christopher H. Logue, Antonio Mazzarelli, Sarah Meisel, Marc Mertens, Janine Michel, Didier Ngabo, Katja Nitzsche, Elisa Pallasch, Livia Victoria Patrono, Jasmine Portmann, Johanna Gabriella Repits, Natasha Y. Rickett, Andreas Sachse, Katrin Singethan, Inês Vitoriano, Rahel L. Yemanaberhan, Elsa G. Zekeng, Trina Racine, Alexander Bello, Amadou Alpha Sall, Ousmane Faye, Oumar Faye, N’Faly Magassouba, Cecelia V. Williams, Victoria Amburgey, Linda Winona, Emily Davis, Jon Gerlach, Frank Washington, Vanessa Monteil, Marine Jourdain, Marion Bererd, Alimou Camara, Hermann Somlare, Abdoulaye Camara, Marianne Gerard, Guillaume Bado, Bernard Baillet, Déborah Delaune, Koumpingnin Yacouba Nebie, Abdoulaye Diarra, Yacouba Savane, Raymond Bernard Pallawo, Giovanna Jaramillo Gutierrez, Natacha Milhano, Isabelle Roger, Christopher J. Williams, Facinet Yattara, Kuiama Lewandowski, James Taylor, Phillip Rachwal, Daniel J. Turner, Georgios Pollakis, Julian A. Hiscox, David A. Matthews, Matthew K. O’ Shea, Andrew McD. Johnston, Duncan Wilson, Emma Hutley, Erasmus Smit, Antonino Di Caro, Roman Wölfel, Kilian Stoecker, Erna Fleischmann, Martin Gabriel, Simon A. Weller, Lamine Koivogui, Boubacar Diallo, Sakoba Keïta, Andrew Rambaut, Pierre Formenty, Stephan Günther, and Miles W. Carroll, "Real-time, portable genome sequencing for Ebola surveillance," Nature vol. 530, no. 7589 pp. 228–232 Feb. 2016.
Joshua S. Bloom, Eric M. Jones, Molly Gasperini, Nathan B. Lubock, Laila Sathe, Chetan Munugala, A. Sina Booeshaghi, Oliver F. Brandenberg, Longhua Guo, James Boocock, Scott W. Simpkins, Isabella Lin, Nathan LaPierre, Duke Hong, Yi Zhang, Gabriel Oland, Bianca Judy Choe, Sukantha Chandrasekaran, Evann E. Hilt, Manish J. Butte, Robert Damoiseaux, Aaron R. Cooper, Yi Yin, Lior Pachter, Omai B. Garner, Jonathan Flint, Eleazar Eskin, Chongyuan Luo, Sriram Kosuri, Leonid Kruglyak, and Valerie A. Arboleda, "Swab-Seq: A high-throughput platform for massively scaled up SARS-CoV-2 testing," medRxiv 2020.
Ebrahim Afshinnekoo, Cem Meydan, Shanin Chowdhury, Dyala Jaroudi, Collin Boyer, Nick Bernstein, Julia M. Maritz, Darryl Reeves, Jorge Gandara, Sagar Chhangawala, Sofia Ahsanuddin, Amber Simmons, Timothy Nessel, Bharathi Sundaresh, Elizabeth Pereira, Ellen Jorgensen, Sergios-Orestis Kolokotronis, Nell Kirchberger, Isaac Garcia, David Gandara, Sean Dhanraj, Tanzina Nawrin, Yogesh Saletore, Noah Alexander, Priyanka Vijay, Elizabeth M. Hénaff, Paul Zumbo, Michael Walsh, Gregory D. O’Mullan, Scott Tighe, Joel T. Dudley, Anya Dunaif, Sean Ennis, Eoghan O’Halloran, Tiago R. Magalhaes, Braden Boone, Angela L. Jones, Theodore R. Muth, Katie Schneider Paolantonio, Elizabeth Alter, Eric E. Schadt, Jeanne Garbarino, Robert J. Prill, Jane M. Carlton, Shawn Levy, and Christopher E. Mason, "Geospatial Resolution of Human and Bacterial Diversity with City-Scale Metagenomics," Cell Systems vol. 1, no. 1 pp. 72–87 Jul. 2015.
Danko, David, Daniela Bezdan, Evan E. Afshin, Sofia Ahsanuddin, Chandrima Bhattacharya, Daniel J. Butler, Kern Rei Chng et al. "A global metagenomic map of urban microbiomes and antimicrobial resistance." Cell (2021).
Charles Schmidt, "Living in a microbial world," Nature Biotechnology 2017.
Mohammed Alser, Nour Almadhoun, Azita Nouri, Can Alkan, and Erman Ayday, "Can you Really Anonymize the Donors of Genomic Data in Today’s Digital World?," In: Garcia-Alfaro J., Navarro-Arribas G., Aldini A., Martinelli F., Suri N. (eds) Data Privacy Management, and Security Assurance. DPM 2015, QASA 2015. Lecture Notes in Computer Science, vol 9481. Springer, Cham.
Syed, Fraz, Haiying Grunenwald, and Nicholas Caruccio. "Next-generation sequencing library preparation: simultaneous fragmentation and tagging using in vitro transposition." Nature Methods 6, no. 11 (2009): i-ii.
Shendure, Jay, and Hanlee Ji. "Next-generation DNA sequencing." Nature biotechnology 26, no. 10 (2008): 1135-1145.
Mohammed Alser, Jeremy Rotman, Dhrithi Deshpande, Kodi Taraszka, Huwenbo Shi, Pelin Icer Baykal, Harry Taegyun Yang, Victor Xue, Sergey Knyazev, Benjamin D. Singer, Brunilda Balliu, David Koslicki, Pavel Skums, Alex Zelikovsky, Can Alkan, Onur Mutlu, and Serghei Mangul. "Technology dictates algorithms: recent developments in read alignment." Genome biology 22, no. 1 (2021): 1-34.
Wan, Yuk Kei, Christopher Hendra, Ploy N. Pratanwanich, and Jonathan Göke. "Beyond sequencing: machine learning algorithms extract biology hidden in Nanopore signal data." Trends in Genetics (2021).
Aaron M. Wenger, Paul Peluso, William J. Rowell, Pi-Chuan Chang, Richard J. Hall, Gregory T. Concepcion, Jana Ebler, Arkarachai Fungtammasan, Alexey Kolesnikov, Nathan D. Olson, Armin Töpfer, Michael Alonge, Medhat Mahmoud, Yufeng Qian, Chen-Shan Chin, Adam M. Phillippy, Michael C. Schatz, Gene Myers, Mark A. DePristo, Jue Ruan, Tobias Marschall, Fritz J. Sedlazeck, Justin M. Zook, Heng Li, Sergey Koren, Andrew Carroll, David R. Rank, and Michael W. Hunkapiller, "Accurate circular consensus long-read sequencing improves variant detection and assembly of a human genome," Nature Biotechnology vol. 37, no. 10 pp. 1155–1162 Oct. 2019.
Sergey Nurk, Sergey Koren, Arang Rhie, Mikko Rautiainen, Andrey V. Bzikadze, Alla Mikheenko, Mitchell R. Vollger, Nicolas Altemose, Lev Uralsky, Ariel Gershman, Sergey Aganezov, Savannah J. Hoyt, Mark Diekhans, Glennis A. Logsdon, Michael Alonge, Stylianos E. Antonarakis, Matthew Borchers, Gerard G. Bouffard, Shelise Y. Brooks, Gina V. Caldas, Haoyu Cheng, Chen-Shan Chin, William Chow, Leonardo G. de Lima, Philip C. Dishuck, Richard Durbin, Tatiana Dvorkina, Ian T. Fiddes, Giulio Formenti, Robert S. Fulton, Arkarachai Fungtammasan, Erik Garrison, Patrick G.S. Grady, Tina A. Graves-Lindsay, Ira M. Hall, Nancy F. Hansen, Gabrielle A. Hartley, Marina Haukness, Kerstin Howe, Michael W. Hunkapiller, Chirag Jain, Miten Jain, Erich D. Jarvis, Peter Kerpedjiev, Melanie Kirsche, Mikhail Kolmogorov, Jonas Korlach, Milinn Kremitzki, Heng Li, Valerie V. Maduro, Tobias Marschall, Ann M. McCartney, Jennifer McDaniel, Danny E. Miller, James C. Mullikin, Eugene W. Myers, Nathan D. Olson, Benedict Paten, Paul Peluso, Pavel A. Pevzner, David Porubsky, Tamara Potapova, Evgeny I. Rogaev, Jeffrey A. Rosenfeld, Steven L. Salzberg, Valerie A. Schneider, Fritz J. Sedlazeck, Kishwar Shafin, Colin J. Shew, Alaina Shumate, Yumi Sims, Arian F. A. Smit, Daniela C. Soto, Ivan Sović, Jessica M. Storer, Aaron Streets, Beth A. Sullivan, Françoise Thibaud-Nissen, James Torrance, Justin Wagner, Brian P. Walenz, Aaron Wenger, Jonathan M. D. Wood, Chunlin Xiao, Stephanie M. Yan, Alice C. Young, Samantha Zarate, Urvashi Surti, Rajiv C. McCoy, Megan Y. Dennis, Ivan A. Alexandrov, Jennifer L. Gerton, Rachel J. O’Neill, Winston Timp, Justin M. Zook, Michael C. Schatz, Evan E. Eichler, Karen H. Miga, Adam M. Phillippy. "https://www.biorxiv.org/content/10.1101/2021.05.26.445798v1", bioArxiv, 2021.
LaPierre, Nathan, Mohammed Alser, Eleazar Eskin, David Koslicki, and Serghei Mangul. "Metalign: efficient alignment-based metagenomic profiling via containment min hash." Genome biology 21, no. 1 (2020): 1-15.
Meyer, F and Fritz, A and Deng, Z-L and Koslicki, D and Gurevich, A and Robertson, G and Alser, M and Antipov, D and Beghini, F and Bertrand, D and others. "Critical Assessment of Metagenome Interpretation - the second round of challenges", bioArxiv, 2021.
Nathan LaPierre, Serghei Mangul, Mohammed Alser, Igor Mandric, Nicholas C. Wu, David Koslicki & Eleazar Eskin. "MiCoP: microbial community profiling method for detecting viral and fungal organisms in metagenomic samples", BMC Genomics, 2019.
Rachel M. Sherman, Juliet Forman, Valentin Antonescu, Daniela Puiu, Michelle Daya, Nicholas Rafaels, Meher Preethi Boorgula, Sameer Chavan, Candelaria Vergara, Victor E. Ortega, Albert M. Levin, Celeste Eng, Maria Yazdanbakhsh, James G. Wilson, Javier Marrugo, Leslie A. Lange, L. Keoki Williams, Harold Watson, Lorraine B. Ware, Christopher O. Olopade, Olufunmilayo Olopade, Ricardo R. Oliveira, Carole Ober, Dan L. Nicolae, Deborah A. Meyers, Alvaro Mayorga, Jennifer Knight-Madden, Tina Hartert, Nadia N. Hansel, Marilyn G. Foreman, Jean G. Ford, Mezbah U. Faruque, Georgia M. Dunston, Luis Caraballo, Esteban G. Burchard, Eugene R. Bleecker, Maria I. Araujo, Edwin F. Herrera-Paz, Monica Campbell, Cassandra Foster, Margaret A. Taub, Terri H. Beaty, Ingo Ruczinski, Rasika A. Mathias, Kathleen C. Barnes, and Steven L. Salzberg, "Assembly of a pan-genome from deep sequencing of 910 humans of African descent," Nature Genetics vol. 51, no. 1 pp. 30–35 Jan. 2019.
Sara Ballouz, Alexander Dobin, and Jesse A. Gillis, "Is it time to change the reference genome?," Genome Biology vol. 20, no. 1 p. 159 Dec. 2019.
Amit Goyal, Hyuk Jung Kwon, Kichan Lee, Reena Garg, Seon Young Yun, Yoon Hee Kim, Sunghoon Lee, and Min Seob Lee, "Ultra-Fast Next Generation Human Genome Sequencing Data Processing Using DRAGEN Bio-IT Processor for Precision Medicine," Open Journal of Genetics 2017.
Burks, Arthur W., Herman H. Goldstine, and John Von Neumann. "Preliminary discussion of the logical design of an electronic computing instrument." In The Origins of Digital Computers, pp. 399-413. Springer, Berlin, Heidelberg, 1982.
A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan, and O. Mutlu, "Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,” ASPLOS, 2018.
Kestor, Gokcen, Roberto Gioiosa, Darren J. Kerbyson, and Adolfy Hoisie. "Quantifying the energy cost of data movement in scientific applications." In 2013 IEEE international symposium on workload characterization (IISWC), pp. 56-65. IEEE, 2013.
D. Pandiyan, and C. Wu. "Quantifying the Energy Cost of Data Movement for Emerging Smart Phone Workloads on Mobile Platforms." IISWC, 2014.
Backurs, Arturs, and Piotr Indyk. "Edit distance cannot be computed in strongly subquadratic time (unless SETH is false)." In Proceedings of the forty-seventh annual ACM symposium on Theory of computing, pp. 51-58. 2015.
Leiserson, C. E., Thompson, N. C., Emer, J. S., Kuszmaul, B. C., Lampson, B. W., Sanchez, D., & Schardl, T. B., "There’s plenty of room at the Top: What will drive computer performance after Moore’s law?". Science, 2020
Hongyi Xin, John Greth, John Emmons, Gennady Pekhimenko, Carl Kingsford, Can Alkan, and Onur Mutlu, "Shifted Hamming distance: a fast and accurate SIMD-friendly filter to accelerate alignment verification in read mapping," Bioinformatics vol. 31, no. 10 pp. 1553–1560 May 2015.
Jones, Neil C. and Pavel Pevzner. "An introduction to bioinformatics algorithms," MIT press, 2004.
Mäkinen, Veli, Djamal Belazzougui, Fabio Cunial, and Alexandru I. Tomescu. "Genome-scale algorithm design," Cambridge University Press, 2015.
Lecture 11 (4.11 Thu.)
Described in detail during lecture 11:
Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt,"Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors" HPCA, 2003.
Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, and Onur Mutlu, "Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture", HPCA 2013
K. K. Chang, P. J. Nair, S. Ghose, D. Lee, M. K. Qureshi, O. Mutlu, "Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM," HPCA 2016
H. Hassan, M. Patel, J. S. Kim, A. G. Yaglikci, N. Vijaykumar, N. Mansourighiasi, S. Ghose, O. Mutlu, "CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability," ISCA 2019
Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, and Onur Mutlu, "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM," ISCA 2012
K. Chang, A. Kashyap, H. Hassan, S. Khan, K. Hsieh, D. Lee, S. Ghose, G. Pekhimenko, T. Li, O. Mutlu, "Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization," SIGMETRICS 2016
D. Lee, Y. Kim, G. Pekhimenko, S. Khan, V. Seshadri, K. Chang, O. Mutlu, "Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case," HPCA 2015
J.S. Kim, M. Patel, H. Hassan, O. Mutlu, ”Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines,” ICCD 2018
D. Lee, S. Khan, L. Subramanian, S. Ghose, R. Ausavarungnirun, G. Pekhimenko, V. Seshadri, O. Mutlu, "Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms,” SIGMETRICS 2017
Suggested (Lecture 11):
Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt,"Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors" MICRO TOP PICKS, 2003.
Onur Mutlu, Hyesoon Kim, and Yale N. Patt, "Techniques for Efficient Processing in Runahead Execution Engines" ISCA 2005, MICRO TOP PICKS 2006
Onur Mutlu, Hyesoon Kim, and Yale N. Patt, "Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns" MICRO, 2005.
David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt,"Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery" MICRO, 2004.
Vivek Seshadri and Onur Mutlu,"In-DRAM Bulk Bitwise Execution Engine" Invited Book Chapter in Advances in Computers, to appear in 2020.
Uksong Kang, Hak-soo Yu, Churoo Park, Hongzhong Zheng, John Halbert, Kuljit Bains, SeongJin Jang, and Joo Sun Choi, "Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling," The Memory Forum 2014
Lecture 12a (5.11 Fri.)
Described in detail during lecture 12a:
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Khan, Vivek Seshadri, Kevin Chang, and Onur Mutlu,"Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case" HPCA, 2015.
Kevin Chang, Abhijith Kashyap, Hasan Hassan, Samira Khan, Kevin Hsieh, Donghyuk Lee, Saugata Ghose, Gennady Pekhimenko, Tianshi Li, and Onur Mutlu,"Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization" SIGMETRICS, 2016.
Donghyuk Lee, Samira Khan, Lavanya Subramanian, Saugata Ghose, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, and Onur Mutlu,"Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms" SIGMETRICS, 2017.
Kevin Chang, A. Giray Yaglikci, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, and Onur Mutlu,"Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms" SIGMETRICS, 2017.
Jeremie S. Kim, Minesh Patel, Hasan Hassan, Lois Orosa, and Onur Mutlu,"D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput" HPCA, 2019.
Ataberk Olgun, Minesh Patel, A. Giray Yaglikci, Haocong Luo, Jeremie S. Kim, F. Nisa Bostanci, Nandita Vijaykumar, Oguz Ergin, and Onur Mutlu,"QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips" ISCA, 2021.
Jeremie S. Kim, Minesh Patel, Hasan Hassan, and Onur Mutlu,"The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern DRAM Devices" HPCA, 2018.
Suggested (Lecture 12a):
Jeremie S. Kim, Minesh Patel, Hasan Hassan, and Onur Mutlu,"Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines" ICCD, 2018.
Skanda Koppula, Lois Orosa, A. Giray Yaglikci, Roknoddin Azizi, Taha Shahroodi, Konstantinos Kanellopoulos, and Onur Mutlu,"EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM" MICRO, 2019.
Yixin Luo, Sriram Govindan, Bikash Sharma, Mark Santaniello, Justin Meza, Aman Kansal, Jie Liu, Badriddine Khessib, Kushagra Vaid, and Onur Mutlu,"Characterizing Application Memory Error Vulnerability to Optimize Datacenter Cost via Heterogeneous-Reliability Memory" DSN, 2014.
Howard David, Chris Fallin, Eugene Gorbatov, Ulf R. Hanebutte, and Onur Mutlu,"Memory Power Management via Dynamic Voltage/Frequency Scaling" ICAC, 2011.
Anup Das, Hasan Hassan, and Onur Mutlu,"VRL-DRAM: Improving DRAM Performance via Variable Refresh Latency" DAC, 2018.
Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar, Vivek Seshadri, Donghyuk Lee, Oguz Ergin, and Onur Mutlu,"ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality" HPCA, 2016.
Yaohua Wang, Arash Tavakkol, Lois Orosa, Saugata Ghose, Nika Mansouri Ghiasi, Minesh Patel, Jeremie S. Kim, Hasan Hassan, Mohammad Sadrosadati, and Onur Mutlu,"Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration" MICRO, 2018.
Kevin Chang, Donghyuk Lee, Zeshan Chishti, Alaa Alameldeen, Chris Wilkerson, Yoongu Kim, and Onur Mutlu, "Improving DRAM Performance by Parallelizing Refreshes with Accesses" HPCA, 2014.
Saugata Ghose, A. Giray Yaglikci, Raghav Gupta, Donghyuk Lee, Kais Kudrolli, William X. Liu, Hasan Hassan, Kevin K. Chang, Niladrish Chatterjee, Aditya Agrawal, Mike O'Connor, and Onur Mutlu,"What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study" SIGMETRICS, 2018.
Lecture 12b (5.11 Fri.)
Described in detail during lecture 12b:
Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrian Cristal, Osman Unsal, and Ken Mai,"Flash Correct-and-Refresh: Retention-Aware Error Management for Increased Flash Memory Lifetime" ICCD, 2012.
Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, and Onur Mutlu, "Error Characterization, Mitigation, and Recovery in Flash Memory Based Solid State Drives" Proceedings of IEEE, 2017.
Arash Tavakkol, Juan Gomez-Luna, Mohammad Sadrosadati, Saugata Ghose, and Onur Mutlu, "MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices" FAST, 2018.
Yoongu Kim, Weikun Yang, and Onur Mutlu,"Ramulator: A Fast and Extensible DRAM Simulator" IEEE Computer Architecture Letters (CAL), March 2015.
Engin Ipek, Onur Mutlu, José F. Martínez, and Rich Caruana, "Self Optimizing Memory Controllers: A Reinforcement Learning Approach" ISCA, 2008.
Suggested (Lecture 12b):
Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, and Onur Mutlu, "Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery" Invited Book Chapter in Inside Solid State Drives, 2018.
Arash Tavakkol, Mohammad Sadrosadati, Saugata Ghose, Jeremie Kim, Yixin Luo, Yaohua Wang, Nika Mansouri Ghiasi, Lois Orosa, Juan G. Luna and Onur Mutlu, "FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives" ISCA, 2018.
Myungsuk Kim, Jisung Park, Geonhee Cho, Yoona Kim, Lois Orosa, Onur Mutlu, and Jihong Kim, "Evanesco: Architectural Support for Efficient Data Sanitization in Modern Flash-Based Storage Systems" ASPLOS, 2020.
Jisung Park, Myungsuk Kim, Myoungjun Chun, Lois Orosa, Jihong Kim, and Onur Mutlu, "Reducing Solid-State Drive Read Latency by Optimizing Read-Retry" ASPLOS, 2021.
Chang Joo Lee, Veynu Narasiman, Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt, "DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems" HPS Technical Report, TR-HPS-2010-002, April 2010.
Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, and Onur Mutlu, "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM" ISCA, 2012.
Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, and Onur Mutlu, "Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture" HPCA, 2013.
Rahul Bera, Konstantinos Kanellopoulos, Anant Nori, Taha Shahroodi, Sreenivas Subramoney, and Onur Mutlu, "Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning" MICRO, 2021.
Lecture 13 (11.11 Thu.)
Described in detail during lecture 13:
Engin Ipek, Onur Mutlu, José F. Martínez, and Rich Caruana, "Self Optimizing Memory Controllers: A Reinforcement Learning Approach" ISCA, 2008.
Thomas Moscibroda and Onur Mutlu, "Memory performance attacks: denial of memory service in multi-core systems," In USENIX Security, 2007.
Onur Mutlu and Thomas Moscibroda, "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors," In MICRO, 2007.
Onur Mutlu and Thomas Moscibroda, "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems," In ISCA, 2008.
Yoongu Kim, Dongsu Han, Onur Mutlu, and Mor Harchol-Balter, "ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers," In HPCA, 2010.
Yoongu Kim, Michael Papamichael, Onur Mutlu, and Mor Harchol-Balter, "Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior," In MICRO, 2010.
Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, and Onur Mutlu, "The Blacklisting Memory Scheduler: Achieving High Performance and Fairness at Low Cost," In ICCD, 2014.
Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, and Onur Mutlu, “BLISS: Balancing Performance, Fairness, and Complexity in Memory Access Scheduling,” IEEE TPDS, 2016.
Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, Onur Mutlu, and Yale N. Patt, "Parallel Application Memory Scheduling," In MICRO, 2011.
Rachata Ausavarungnirun, Kevin Chang, Lavanya Subramanian, Gabriel Loh, and Onur Mutlu, “Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems,” In ISCA, 2012.
Suggested (Lecture 13):
Rahul Bera, Konstantinos Kanellopoulos, Anant Nori, Taha Shahroodi, Sreenivas Subramoney, and Onur Mutlu, "Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning" MICRO, 2021.
Onur Mutlu, "Intelligent Architectures for Intelligent Computing Systems," In DATE, 2021.
Onur Mutlu, "Memory-Centric Computing Systems" Invited Tutorial at 66th International Electron Devices Meeting (IEDM), Virtual, 12 December 2020.
Seongbeom Kim, Dhruba Chandra, and Yan Solihin, "Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture," In PACT, 2004.
Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter Mattson, and John D. Owens, "Memory Access Scheduling, In ISCA, 2000.
Boris Grot, Stephen W. Keckler, and Onur Mutlu, "Preemptive Virtual Clock: A Flexible, Efficient, and Cost-effective QoS Scheme for Networks-on-Chip," In MICRO, 2009.
Onur Mutlu and Thomas Moscibroda, "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers," IEEE Micro (Micro Top Picks), 2009.
Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, and Thomas Moscibroda, “Reducing Memory Interference in Multicore Systems via Application-aware Memory Channel Partitioning,” In MICRO, 2011.
Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, and Onur Mutlu, "MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems," In HPCA, 2013.
Lavanya Subramanian, Vivek Seshadri, Arnab Ghosh, Samira Khan, and Onur Mutlu, "The Application Slowdown Model: Quantifying and Controlling the Impact of Inter-Application Interference at Shared Caches and Main Memory," In MICRO, 2015.
Hiroyuki Usui, Lavanya Subramanian, Kevin Kai-Wei Chang, and Onur Mutlu, “DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators,” ACM TACO, 2016.
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Patt, "Prefetch-Aware Shared Resource Management for Multi-Core Systems," In ISCA, 2011.
Chang Joo Lee, Veynu Narasiman, Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt, "DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems" HPS Technical Report, TR-HPS-2010-002, April 2010.
Jishen Zhao, Onur Mutlu, and Yuan Xie, "FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems," In MICRO, 2014.
Adwait Jog, Onur Kayiran, Ashutosh Pattnaik, Mahmut T. Kandemir, Onur Mutlu, Ravishankar Iyer, and Chita R. Das, "Exploiting Core Criticality for Enhanced GPU Performance", In SIGMETRICS, 2016.
Hyoseung Kim, Dionisio de Niz, Bjorn Andersson, Mark Klein, Onur Mutlu, and Ragunathan (Raj) Rajkumar, "Bounding Memory Interference Delay in COTS-based Multi-Core Systems," In RTAS, 2014.
Lecture 14a (12.11 Fri.)
Described in detail during lecture 14a:
Onur Mutlu and Thomas Moscibroda, "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors," In MICRO, 2007
Onur Mutlu and Thomas Moscibroda, "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems," In ISCA, 2008
Onur Mutlu and Thomas Moscibroda, "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers," IEEE Micro (Micro Top Picks), 2009
Yoongu Kim, Dongsu Han, Onur Mutlu, and Mor Harchol-Balter, "ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers," In HPCA, 2010
Yoongu Kim, Michael Papamichael, Onur Mutlu, and Mor Harchol-Balter, "Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior," In MICRO, 2010
Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, and Onur Mutlu, "The Blacklisting Memory Scheduler: Achieving High Performance and Fairness at Low Cost," In ICCD, 2014
Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, and Onur Mutlu, “BLISS: Balancing Performance, Fairness, and Complexity in Memory Access Scheduling,” IEEE TPDS, 2016
Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, Onur Mutlu, and Yale N. Patt, "Parallel Application Memory Scheduling," In MICRO, 2011
Jose A. Joao, M. Aater Suleman, Onur Mutlu, and Yale N. Patt, "Bottleneck Identification and Scheduling in Multithreaded Applications". ASPLOS'12
Jose A. Joao, M. Aater Suleman, Onur Mutlu, and Yale N. Patt, "Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs". ISCA'13
Rachata Ausavarungnirun, Kevin Chang, Lavanya Subramanian, Gabriel Loh, and Onur Mutlu, “Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems,” In ISCA, 2012
Suggested (lecture 14a):
Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, and Thomas Moscibroda, “Reducing Memory Interference in Multicore Systems via Application-aware Memory Channel Partitioning,” In MICRO, 2011
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Patt, "Prefetch-Aware Shared Resource Management for Multi-Core Systems," In ISCA, 2011
Chang Joo Lee, Veynu Narasiman, Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt, "DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems", HPS Technical Report, 2010
Jishen Zhao, Onur Mutlu, and Yuan Xie, "FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems," In MICRO, 2014
E. Ebrahimi, C. J. Lee, O. Mutlu, and Y. N. Patt, "Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems," ASPLOS 2010
Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, and Onur Mutlu, "MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems," In HPCA, 2013
Lavanya Subramanian, Vivek Seshadri, Arnab Ghosh, Samira Khan, and Onur Mutlu, "The Application Slowdown Model: Quantifying and Controlling the Impact of Inter-Application Interference at Shared Caches and Main Memory," In MICRO, 2015
Hiroyuki Usui, Lavanya Subramanian, Kevin Kai-Wei Chang, and Onur Mutlu, “DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators,” ACM TACO, 2016
K. Chang, R. Ausavarungnirun, C. Fallin, and O. Mutlu, "HAT: Heterogeneous Adaptive Throttling for On-Chip Networks," SBAC-PAD, 2012
G. Nychis, C. Fallin, T. Moscibroda, O. Mutlu, and S. Seshan, "On-Chip Networks from a Networking Perspective: Congestion and Scalability in Many-core Interconnects," SIGCOMM, 2012
R. Das, R. Ausavarungnirun, O. Mutlu, A. Kumar, and M. Azimi, "Application-to-Core Mapping Policies to Reduce Memory System Interference in Multi-Core Systems," HPCA 2013
H. Wang, C. Isci, L. Subramanian, J. Choi, D. Qian, and O. Mutlu, "A-DRM: Architecture-aware Distributed Resource Management of Virtualized Clusters," VEE 2015
Lecture 14b (12.11 Fri.)
Described in detail during lecture 14b:
HanBin Yoon, Justin Meza, Naveen Muralimanohar, Norman P. Jouppi, and Onur Mutlu, "Efficient Data Mapping and Buffering Techniques for Multi-Level Cell Phase-Change Memories" TACO 2014
E. Kultursay, M. Kandemir, A. Sivasubramaniam, and O. Mutlu, "Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative" ISPASS 2013
Moinuddin K. Qureshi, Viji Srinivasan, and Jude A. Rivers "Scalable High-Performance Main Memory System Using Phase-Change Memory Technology" ISCA 2009
H. Yoon, J. Meza, R. Ausavarungnirun, R. Harding, and O. Mutlu, "Row Buffer Locality Aware Caching Policies for Hybrid Memories" ICCD 2012
Y. Li, S. Ghose, J. Choi, J. Sun, H. Wang, and O. Mutlu, "Utility-Based Hybrid Memory Management" CLUSTER 2017
J. Meza, J. Chang, H. Yoon, O. Mutlu, and P. Ranganathan, "Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management" CAL 2012
X. Yu, C. J. Hughes, N. Satish, O. Mutlu, and S. Devadas,"Banshee: Bandwidth-Efficient DRAM Caching via Software/Hardware Cooperation" MICRO 2017
S. Li, C. Xu, Q. Zou, J. Zhao, Y. Lu, and Y. Xie, "Pinatubo: A Processing-in-Memory Architecture for Bulk Bitwise Operations in Emerging Non-volatile Memories," DAC, 2016
J. Meza, Y. Luo, S. Khan, J. Zhao, Y. Xie, and O. Mutlu, "A Case for Efficient Hardware-Software Cooperative Management of Storage and Memory" WEED 2013
J. Ren, J. Zhao, S. Khan, J., Y. Wu, and O. Mutlu, "ThyNVM: Enabling Software-Transparent Crash Consistency in Persistent Memory Systems," MICRO 2015
Suggested (Lecture 14b):
B.C. Lee, E. Ipek, O. Mutlu, D. Burger, "Architecting Phase Change Memory as a Scalable DRAM Alternative," ISCA 2009
B.C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. Burger, "Phase Change Technology and the Future of Main Memory," MICRO Top Picks 2010
V. Seshadri, K. Hsieh, A. Boroumand, D. Lee, M.A. Kozuch, O.Mutlu, P.B. Gibbons, T.C. Mowry, "Fast Bulk Bitwise AND and OR in DRAM," IEEE CAL, 2015.
V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M.A. Kozuch, O. Mutlu, P.B. Gibbons, T.C. Mowry, “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” MICRO, 2017.
V. Seshadri and O. Mutlu, "In-DRAM Bulk Bitwise Execution Engine," Invited Book Chapter in Advances in Computers, to appear in 2020.
N. Hajinazar, G. F. Oliveira, S. Gregorio, J. D. Ferreira, N. M. Ghiasi, M. Patel, M. Alser, S. Ghose, J. Gomez-Luna, and O. Mutlu, “SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM,” ASPLOS, 2021.
H. Chauhan, I. Calciu, V. Chidambaram, E. Schkufza, O. Mutlu, and P. Subrahmanyam, "NVMove: Helping Programmers Move to Byte-Based Persistence," INFLOW 2016
Y. Lu, J. Shu, L. Sun, and Onur Mutlu, "Loose-Ordering Consistency for Persistent Memory," ICCD 2014
Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, Onur Mutlu, ”Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives”, PIEEE, 2017
Lecture 15a (18.11 Thu.)
Described in detail during Lecture 15a:
Rahul Bera, Konstantinos Kanellopoulos, Anant V. Nori, Taha Shahroodi, Sreenivas Subramoney, Onur Mutlu, "Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning," MICRO'21
Suggested (Lecture 15c):
Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson and Zeshan Chishti, "Path Confidence based Lookahead Prefetching," MICRO'16
Rahul Bera, Anant V. Nori, Onur Mutlu, and Sreenivas Subramoney,"DSPatch: Dual Spatial Pattern Prefetcher," in MICRO'19
Mohammad Bakhshalipour, Mehran Shakerinava, Pejman Lotfi-Kamran, Hamid Sarbazi-Azad, "Bingo Spatial Data Prefetcher," in HPCA'19
Mehran Shakerinava, Mohammad Bakhshalipour, Pejman Lotfi-Kamran, Hamid Sarbazi-Azad, "Multi-Lookahead Offset Prefetching," in ISCA'19
Eshan Bhatia, Gino Chacon, Seth Pugsley, Elvira Teran, Paul V. Gratz, Daniel A. Jiménez"Perceptron-Based Prefetch Filtering" in ISCA'19
Lecture 15b (18.11 Thu.)
Described in detail during Lecture 15b:
Amirali Boroumand, Saugata Ghose, Berkin Akin, Ravi Narayanaswami, Geraldo F. Oliveira, Xiaoyu Ma, Eric Shiu, and Onur Mutlu,"Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks," PACT'21
Suggested (Lecture 15c):
Y.-H. Chen, T.-J Yang, J. Emer, V. Sze, "Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices," JETCAS'19
N. P. Jouppi+, "In-Datacenter Performance Analysis of a Tensor Processing Unit," ISCA'17
A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan, and O. Mutlu, "Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks," ASPLOS'18
Lecture 15c (18.11 Thu.)
Described in detail during Lecture 15c:
Lois Orosa, Yaohua Wang, Mohammad Sadrosadati, Jeremie S. Kim, Minesh Patel, Ivan Puddu, Haocong Luo, Kaveh Razavi, Juan Gomez-Luna, Hasan Hassan, Nika Mansouri-Ghiasi, Saugata Ghose, and Onur Mutlu, "CODIC: A Low-cost Substrate for Enabling Custom in-DRAM Functionalities and Optimizations," ISCA’21
Suggested (Lecture 15c):
Lois Orosa, Yaohua Wang, Mohammad Sadrosadati, Jeremie S. Kim, Minesh Patel, Ivan Puddu, Haocong Luo, Kaveh Razavi, Juan Gomez-Luna, Hasan Hassan, Nika Mansouri-Ghiasi, Saugata Ghose, and Onur Mutlu, "CODIC: A Low-cost Substrate for Enabling Custom in-DRAM Functionalities and Optimizations," arXiv’21
Hassan, H., Vijaykumar, N., Khan, S., Ghose, S., Chang, K., Pekhimenko, G., Lee, D., Ergin, O. and Mutlu, O , "SoftMC: A flexible and practical open-source infrastructure for enabling experimental DRAM studies," HPCA’17
Lecture 16a (19.11 Fri.)
Suggested (Lecture 16a):
Hassan, Hasan, Yahya Can Tugrul, Jeremie S. Kim, Victor Van der Veen, Kaveh Razavi, and Onur Mutlu, "Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications," MICRO'21
, Hassan, H., Vijaykumar, N., Khan, S., Ghose, S., Chang, K., Pekhimenko, G., Lee, D., Ergin, O. and Mutlu, O."SoftMC: A flexible and practical open-source infrastructure for enabling experimental DRAM studies," HPCA'17
, Patel, M., Kim, J.S. and Mutlu, O. "The reach profiler (REAPER) enabling the mitigation of DRAM retention failures via profiling at aggressive conditions.The reach profiler (REAPER) enabling the mitigation of DRAM retention failures via profiling at aggressive conditions.," ISCA'17
Lecture 16b (19.11 Fri.)
Suggested (Lecture 16b):
, Lois Orosa, Abdullah Giray Yaglikci, Haocong Luo, Ataberk Olgun, Jisung Park, Hasan Hassan, Minesh Patel, Jeremie S. Kim, and Onur Mutlu "A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses," MICRO’21
Hassan, H., Vijaykumar, N., Khan, S., Ghose, S., Chang, K., Pekhimenko, G., Lee, D., Ergin, O. and Mutlu, O. , "SoftMC: A flexible and practical open-source infrastructure for enabling experimental DRAM studies," HPCA’17
Lecture 16c (19.11 Fri.)
Suggested (Lecture 16c):
A. Giray Yaglikci, Minesh Patel, Jeremie S. Kim, Roknoddin Azizi, Ataberk Olgun, Lois Orosa, Hasan Hassan, Jisung Park, Konstantinos Kanellopoulos, Taha Shahroodi, Saugata Ghose, and Onur Mutlu , "BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows," HPCA’21
Hassan, H., Vijaykumar, N., Khan, S., Ghose, S., Chang, K., Pekhimenko, G., Lee, D., Ergin, O. and Mutlu, O , "SoftMC: A flexible and practical open-source infrastructure for enabling experimental DRAM studies," HPCA’17
Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, and Onur Mutlu, "Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors," ISCA’14
Jeremie S. Kim, Minesh Patel, A. Giray Yaglikci, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu, "Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques," ISCA’20
Lecture 16d (19.11 Fri.)
Suggested (Lecture 16d):
Minesh Patel, Geraldo F. de Oliveira Jr., and Onur Mutlu, "HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes," MICRO’21
Kline, D., Zhang, J., Melhem, R. and Jones, A.K., "Flower and fame: A low overhead bit-level fault-map and fault-tolerance approach for deeply scaled memories," HPCA’20
Nair, P.J., Kim, D.H. and Qureshi, M.K., "ArchShield: Architectural framework for assisting DRAM scaling by tolerating high error rates," ISCA’13
Minesh Patel, Jeremie S. Kim, Taha Shahroodi, Hasan Hassan, and Onur Mutlu, "Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics," MICRO’20
Lecture 17a (25.11 Fri.)
Described in detail during lecture 17a:
H. Yoon, J. Meza, R. Ausavarungnirun, R. Harding, and O. Mutlu, "Row Buffer Locality Aware Caching Policies for Hybrid Memories" ICCD 2012
Y. Li, S. Ghose, J. Choi, J. Sun, H. Wang, and O. Mutlu, "Utility-Based Hybrid Memory Management" CLUSTER 2017
J. Meza, J. Chang, H. Yoon, O. Mutlu, and P. Ranganathan, "Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management" CAL 2012
J. Meza, Y. Luo, S. Khan, J. Zhao, Y. Xie, and O. Mutlu, "A Case for Efficient Hardware-Software Cooperative Management of Storage and Memory" WEED 2013
J. Ren, J. Zhao, S. Khan, J., Y. Wu, and O. Mutlu, "ThyNVM: Enabling Software-Transparent Crash Consistency in Persistent Memory Systems," MICRO 2015
Suggested (Lecture 17a):
B.C. Lee, E. Ipek, O. Mutlu, D. Burger, "Architecting Phase Change Memory as a Scalable DRAM Alternative," ISCA 2009
B.C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. Burger, "Phase Change Technology and the Future of Main Memory," MICRO Top Picks 2010
HanBin Yoon, Justin Meza, Naveen Muralimanohar, Norman P. Jouppi, and Onur Mutlu, "Efficient Data Mapping and Buffering Techniques for Multi-Level Cell Phase-Change Memories" TACO 2014
E. Kultursay, M. Kandemir, A. Sivasubramaniam, and O. Mutlu, "Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative" ISPASS 2013
X. Yu, C. J. Hughes, N. Satish, O. Mutlu, and S. Devadas,"Banshee: Bandwidth-Efficient DRAM Caching via Software/Hardware Cooperation" MICRO 2017
V. Seshadri, K. Hsieh, A. Boroumand, D. Lee, M.A. Kozuch, O.Mutlu, P.B. Gibbons, T.C. Mowry, "Fast Bulk Bitwise AND and OR in DRAM," IEEE CAL, 2015.
V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M.A. Kozuch, O. Mutlu, P.B. Gibbons, T.C. Mowry, “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” MICRO, 2017.
N. Hajinazar, G. F. Oliveira, S. Gregorio, J. D. Ferreira, N. M. Ghiasi, M. Patel, M. Alser, S. Ghose, J. Gomez-Luna, and O. Mutlu, “SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM,” ASPLOS, 2021.
S. Li, C. Xu, Q. Zou, J. Zhao, Y. Lu, and Y. Xie, "Pinatubo: A Processing-in-Memory Architecture for Bulk Bitwise Operations in Emerging Non-volatile Memories," DAC, 2016.
A. Shafiee, A. Nag, N. Muralimanohar, R. Balasubramonian, J. P. Strachan, M. Hu, R. S. Williams, and V. Srikumar, "ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars," ISCA, 2016.
P. Chi, S. Li, C. Xu, T. Zhang, J. Zhao, Y. Liu, Y. Wang, and Y. Xie, “PRIME: A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Min Memory”, ISCA, 2016.} * {{M. Prezioso, F. Merrikh-Bayat, B. D. Hoskins, G. C. Adam, K. K. Likharev & D. B. Strukov|“Training and Operation of an Integrated Neuromorphic Network based on Metal-Oxide Memristors,” Nature, 2015.
S. Ambrogio, P. Narayanan, H. Tsai, R. M. Shelby, I. Boybat, C. di Nolfo, S. Sidler, M. Giordano, M. Bodini, N. C. P. Farinha, B. Killeen, C. Cheng, Y. Jaoudi & G. W. Burr, “Equivalent-accuracy accelerated neural-network training using analogue memory,” Nature, 2018.
H. Chauhan, I. Calciu, V. Chidambaram, E. Schkufza, O. Mutlu, and P. Subrahmanyam, "NVMove: Helping Programmers Move to Byte-Based Persistence," INFLOW 2016
Y. Lu, J. Shu, L. Sun, and O. Mutlu, "Loose-Ordering Consistency for Persistent Memory"
Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo, and O. Mutlu,"Error Characterization, Mitigation, and Recovery in Flash Memory Based Solid State Drives"Proceedings of the IEEE, 2017
Lecture 17b (25.11 Fri.)
Described in detail during lecture 17b:
G. M. Amdahl, "Validity of the single processor approach to achieving large scale computing capabilities," AFIPS 1967
Suggested (Lecture 17b):
M. A. Suleman, O. Mutlu, M. K. Qureshi, and Y. N. Patt, "Accelerating critical section execution with asymmetric multi-core architectures," ASPLOS, 2009.
Jose A. Joao, M. Aater Suleman, Onur Mutlu, and Yale N. Patt, "Bottleneck Identification and Scheduling in Multithreaded Applications". ASPLOS, 2012.
J. A. Joao, M. A. Suleman, O. Mutlu, and Y. N. Patt, "Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs". ISCA'13
E. Grochowski, R. Ronen, J. Shen, and H. Wang, "Best of Both Latency and Throughput". ICCD 2004
M. A. Suleman, O. Mutlu, J. A. Joao, Khubaib, and Y. N. Patt, "Data Marshaling for Multi-core Systems", ISCA 2010
J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy, "POWER4 System Microarchitecture". IBM J R&D 2002
Ron Kalla, Balaram Sinharoy, and Joel M. Tendler, "IBM Power5 Chip: A Dual-Core Multithreaded Processor". IEEE Micro 2004
P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32-Way Multithreaded Sparc Processor", IEEE Micro 2005
Lecture 18 (26.11 Fri.)
Described in detail during lecture 18:
M. A. Suleman, O. Mutlu, M. K. Qureshi, and Y. N. Patt, "Accelerating critical section execution with asymmetric multi-core architectures," ASPLOS'09
Jose A. Joao, M. Aater Suleman, Onur Mutlu, and Yale N. Patt, "Bottleneck Identification and Scheduling in Multithreaded Applications". ASPLOS'12
Jose A. Joao, M. Aater Suleman, Onur Mutlu, and Yale N. Patt, "Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs". ISCA'13
M. Aater Suleman, Onur Mutlu, Jose A. Joao, Khubaib, and Yale N. Patt, "Data Marshaling for Multi-core Architectures". ISCA'10
Suggested (Lecture 18):
Grochowski, Ed, Ronny Ronen, John Shen, and Hong Wang. "Best of both latency and throughput". ICCD'04.
Kumar Rakesh, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, and Dean M. Tullsen. "Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction". MICRO'03.
Annavaram, Murali, Edward Grochowski, and John Shen. "Mitigating Amdahl's law through EPI throttling". ISCA'05.
Onur Mutlu."Asymmetry Everywhere (with Automatic Resource Management)". NSF ACAR'10
Lozi, Jean-Pierre, Florian David, Gaël Thomas, Julia Lawall, and Gilles Muller. "Remote core locking: Migrating critical-section execution to improve the performance of multithreaded applications." In 2012 {USENIX} Annual Technical Conference ({USENIX}{ATC} 12), pp. 65-76. 2012.
Lecture 19a (2.12 Thu.)
Described in detail during lecture 19a:
G.M. Amdahl, “Validity of the single processor approach to achieving large scale computing capabilities,” AFIPS 1967
M.J. Flynn, “Very high-speed computing systems,” Proc. of IEEE 1966
M. D. Hill, N. P. Jouppi, G. S. Sohi, "Multiprocessors and Multicomputers,” pp. 551-560 in Readings in Computer Architecture
M. D. Hill, N. P. Jouppi, G. S. Sohi, "Dataflow and Multithreading," pp. 309-314 in Readings in Computer Architecture
B. Lee and A.R. Hurson, "Dataflow Architectures and Multithreading," IEEE Computer 1994
L. Lamport. "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs". IEEE Trans. 1979
M. S. Papamarcos and J. H. Patel, "A low-overhead coherence solution for multiprocessors with private cache memories," ISCA 1984
Culler and Singh, Parallel Computer Architecture, Chapter 5.1 (pp 269 – 283)
Culler and Singh, Parallel Computer Architecture, Chapter 5.3 (pp 291 – 305)
P&H, Computer Organization and Design, Chapter 5.8 (pp 534 – 538 in 4th and 4th revised eds.)
Suggested (Lecture 19a):
J. E. Thornton, “CDC 6600: Design of a Computer,” 1970
B. Smith, “A pipelined, shared resource MIMD computer,” ICPP 1978
M. A. Suleman, O. Mutlu, M. K. Qureshi, and Y. N. Patt, "Accelerating critical section execution with asymmetric multi-core architectures," ASPLOS'09
Jose A. Joao, M. Aater Suleman, Onur Mutlu, and Yale N. Patt, "Bottleneck Identification and Scheduling in Multithreaded Applications". ASPLOS'12
Jose A. Joao, M. Aater Suleman, Onur Mutlu, and Yale N. Patt, "Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs". ISCA'13
M. A. Suleman, O. Mutlu, J. A. Joao, Khubaib, and Y. N. Patt, "Data Marshaling for Multi-core Systems", ISCA 2010
Lecture 19b (2.12 Thu.)
Described in detail during lecture 19b:
L. Lamport. "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs," IEEE TC, 1979.
K. Gharachorloo, A. Gupta, and J. Hennessy, "Two Techniques to Enhance the Performance of Memory Consistency Models," in ICPP, 1991.
Suggested (Lecture 19b):
S. Koppula, L. Orosa, A. G. Yaglikci, R. Azizi, T. Shahroodi, K. Kanellopoulos, and O. Mutlu, "EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM," in MICRO, 2019.
Y. Luo, S. Govindan, B. Sharma, M. Santaniello, J. Meza, A. Kansal, J. Liu, B. Khessib, K. Vaid, and O. Mutlu, "Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory," in DSN, 2014.
K. Gharachorloo, D. Lenoski, J. Laudon, P. Gibbons, A. Gupta, and J. Hennessy, "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors," in ISCA, 1990.
L. Ceze, J. Tuck, P. Montesinos, and J. Torrellas, "BulkSC: bulk enforcement of sequential consistency," in ISCA, 2007.
E. W. Dijkstra, "Cooperating Sequential Processes," 1965
Lecture 20 (3.12 Fri.)
Described in detail during lecture 22
Culler and Singh, Parallel Computer Architecture, Chapter 5.3 (pp 291-305)
P&H, Computer Organization and Design, Chapter 5.10 (pp 466-470)
M. S. Papamarcos and J. H. Patel, "A low-overhead coherence solution for multiprocessors with private cache memories," ISCA 1984
A. Boroumand, S. Ghose, M. Patel, H. Hassan, B. Lucia, R. Ausavarungnirun, K. Hsieh, N. Hajinazar, K.T. Malladi, H. Zheng, and O. Mutlu, "CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators," ISCA 2019
Suggested (lecture 20):
L. M. Censier and P. Feautrier, "A new solution to coherence problems in multicache systems," IEEE Trans. Computers, 1978
J. R. Goodman, "Using cache memory to reduce processor-memory traffic," ISCA 1983
J. Laudon and D. Lenoski, "The SGI Origin: A ccNUMA Highly Scalable Server," ISCA 1997
M. Martin, M. D. Hill, and D. A. Wood, "Token coherence: decoupling performance and correctness," ISCA 2003
J. Baer and W. Wang, "On the inclusion properties for multi-level cache hierarchies," ISCA 1988
A. Boroumand, S. Ghose, M. Patel, H. Hassan, B. Lucia, K. Hsieh, K.T. Malladi, H. Zheng, and O. Mutlu, "LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory," CAL 2016
Lecture 21 (09.12 Thu.)
Required Readings (lecture 21):
T. Moscibroda and O. Mutlu, "A Case for Bufferless Routing in On-Chip Networks", ISCA 2009
Das, Reetuparna, Onur Mutlu, Thomas Moscibroda, and Chita R. Das., "Aergia: Exploiting packet latency slack in on-chip networks", ISCA, 2010.
Suggested (lecture 21):
Das, Reetuparna, Onur Mutlu, Thomas Moscibroda, and Chita R. Das. "Application-aware prioritization mechanisms for on-chip networks", MICRO, 2009.
Dally, William J., and Brian Towles. "Route packets, not wires: on-chip inteconnection networks", DAC, 2001.
Patel, Janak H. "Processor-memory interconnections for multiprocessors", ISCA, 1979.
Gottlieb, Allan, Ralph Grishman, Clyde P. Kruskal, Kevin P. McAuliffe, Larry Rudolph, and Marc Snir. "The NYU Ultracomputer? Designing an MIMD Shared Memory Parallel Computer", IEEE Transactions on computers, 1983.
Lecture 22 (10.12 Fri.)
Described in detail during lecture 22:
Thomas Moscibroda and Onur Mutlu, "A Case for Bufferless Routing in On-Chip Networks", ISCA, 2009.
Chris Fallin, Chris Craik, and Onur Mutlu, "CHIPPER: A Low-Complexity Bufferless Deflection Router", HPCA, 2011.
Chris Fallin, Greg Nazario, Xiangyao Yu, Kevin Chang, Rachata Ausavarungnirun, and Onur Mutlu, "MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect", NOCS, 2012.
Suggested (lecture 22):
Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Chang, Greg Nazario, Reetuparna Das, Gabriel Loh, and Onur Mutlu, "A Case for Hierarchical Rings with Deflection Routing: An Energy-Efficient On-Chip Communication Substrate", PARCO, 2016 (arXiv version in the link).
Boris Grot, Joel Hestness, Stephen W. Keckler, and Onur Mutlu, "Express Cube Topologies for On-Chip Interconnects", HPCA, 2009.
George Nychis, Chris Fallin, Thomas Moscibroda, Onur Mutlu, and Srinivasan Seshan, "On-Chip Networks from a Networking Perspective: Congestion and Scalability in Many-core Interconnects", SIGCOMM, 2012.
George Nychis, Chris Fallin, Thomas Moscibroda, and Onur Mutlu, "Next Generation On-Chip Networks: What Kind of Congestion Control Do We Need?", HOTNETS, 2010.
Chris Fallin, Greg Nazario, Xiangyao Yu, Kevin Chang, Rachata Ausavarungnirun, and Onur Mutlu, "Bufferless and Minimally-Buffered Deflection Routing", Routing Algorithms in Network-on-Chip, 2014.
Asit K. Mishra, Onur Mutlu, and Chita R. Das, "A Heterogeneous Multiple Network-on-Chip Design: An Application-Aware Approach", DAC, 2013.
Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Chang, Greg Nazario, Reetuparna Das, Gabriel Loh, and Onur Mutlu, "Design and Evaluation of Hierarchical Rings with Deflection Routing", SBAC-PAD, 2014.
Kevin Chang, Rachata Ausavarungnirun, Chris Fallin, and Onur Mutlu, "HAT: Heterogeneous Adaptive Throttling for On-Chip Networks", SBAC-PAD, 2012.
Rachata Ausavarungnirun and Onur Mutlu, "Energy-Efficient Deflection-based On-chip Networks: Topology, Routing, Flow Control", arXiv, 2021.
Lecture 23 (16.12 Fri.)
Suggested (lecture 23):
M.J. Flynn, “Very high-speed computing systems,” Proc. of IEEE 1966
J.A.Fisher, "Very Long Instruction Word architectures and the ELI-512,” ISCA 1983
R.M. Russell, "The CRAY-1 computer system,” CACM 1978
B.R. Rau, "Pseudo-randomly interleaved memory,” ISCA 1991
A. Peleg and U. Weiser, "MMX technology extension to the Intel architecture,” IEEE Micro 1996
E. Lindholm, J. Nickolls, S. Oberman, and J. Montrym, "NVIDIA Tesla: A Unified Graphics and Computing Architecture,” IEEE Micro 2008
W.W.L. Fung, I. Sham, G. Yuan, and T.M. Aamodt, "Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow," MICRO 2007
Lecture 24a (23.12 Thu.)
Described in detail during Lecture 24a:
Ataberk Olgun, Minesh Patel, A. Giray Yaglikci, Haocong Luo, Jeremie S. Kim, F. Nisa Bostanci, Nandita Vijaykumar, Oguz Ergin, and Onur Mutlu,"QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips" ISCA, 2021.
Suggested (lecture 24a):
Jeremie S. Kim, Minesh Patel, Hasan Hassan, Lois Orosa, and Onur Mutlu, "D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput". Proceedings of the 25th International Symposium on High-Performance Computer Architecture (HPCA), Washington, DC, USA, February 2019.
Lecture 24b (23.12 Thu.)
Described in detail during Lecture 24b:
Christina Giannoula, Nandita Vijaykumar, Nikela Papadopoulou, Vasileios Karakostas, Ivan Fernandez, Juan Gómez-Luna, Lois Orosa, Nectarios Koziris, Georgios Goumas, and Onur Mutlu, "SynCron: Efficient Synchronization Support for Near-DataProcessing Architectures". Proceedings of the 27th International Symposium on High-Performance Computer Architecture (HPCA), Virtual, February-March 2021.
Suggested (lecture 24b):
A. Boroumand, S. Ghose, M. Patel, H. Hassan, B. Lucia, R. Ausavarungnirun, K. Hsieh, N. Hajinazar, K.T. Malladi, H. Zheng, and O. Mutlu, "CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators," ISCA 2019
A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan, and O. Mutlu, "Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,” ASPLOS, 2018.
Kevin Hsieh, Samira Khan, Nandita Vijaykumar, Kevin K. Chang, Amirali Boroumand, Saugata Ghose, and Onur Mutlu, "Accelerating Pointer Chasing in 3D-Stacked Memory: Challenges, Mechanisms, Evaluation," ICCD, 2016.
Z. Liu, I. Calciu, M. Herlihy, and O. Mutlu, "Concurrent Data Structures for Near-Memory Computing," SPAA 2017
M. A. Suleman, O. Mutlu, M. K. Qureshi, and Y. N. Patt, "Accelerating critical section execution with asymmetric multi-core architectures," ASPLOS'09
Jose A. Joao, M. Aater Suleman, Onur Mutlu, and Yale N. Patt, "Bottleneck Identification and Scheduling in Multithreaded Applications". ASPLOS'12
M. Aater Suleman, Onur Mutlu, Jose A. Joao, Khubaib, and Yale N. Patt, "Data Marshaling for Multi-core Architectures". ISCA'10
Jose A. Joao, M. Aater Suleman, Onur Mutlu, and Yale N. Patt, "Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs". ISCA'13
Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, Onur Mutlu, and Yale N. Patt, "Parallel Application Memory Scheduling," In MICRO, 2011.
Lecture 24c (23.12 Thu.)
Described in detail during Lecture 24c:
N. Hajinazar, G. F. Oliveira, S. Gregorio, J. D. Ferreira, N. M. Ghiasi, M. Patel, M. Alser, S. Ghose, J. Gomez-Luna, and O. Mutlu, “SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM,” ASPLOS, 2021.
Suggested (lecture 24c):
V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M.A. Kozuch, O. Mutlu, P.B. Gibbons, T.C. Mowry, “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” MICRO, 2017.
V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, M.A. Kozuch, P.B. Gibbons, T.C. Mowry, "RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization," MICRO, 2013.
Y. Wang, L. Orosa, X. Peng, Y. Guo, S. Ghose, M. Patel, J. S. Kim, J. G. Luna, M. Sadrosadati, N. M. Ghiasi, and O. Mutlu, "FIGARO: Improving System Performance via Fine-Grained In- DRAM Data Relocation and Caching", MICRO 2020
F. Gao, G. Tziantzioulis, D. Wentzlaff, "ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs," MICRO, 2019.
Lecture 24d (23.12 Thu.)
Described in detail during Lecture 24d:
G. Singh, D. Diamantopoulos, C. Hagleitner, J. Gómez-Luna, S. Stuijk, O. Mutlu, and H. Corporaal, "NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling," FPL, 2020
Suggested (lecture 24d):
Gagandeep Singh, Mohammed Alser, Damla Senol Cali, Dionysios Diamantopoulos, Juan Gomez-Luna, Henk Corporaal, Onur Mutlu, “FPGA-Based Near-Memory Acceleration of Modern Data-Intensive Applications“ IEEE Micro, 2021.
Gagandeep Singh, Juan Gomez-Luna, Giovanni Mariani, Geraldo F. Oliveira, Stefano Corda, Sander Stujik, Onur Mutlu, and Henk Corporaal, "NAPEL: Near-Memory Computing Application Performance Prediction via Ensemble Learning," in DAC 2019.
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mnika
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