schedule
Differences
This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revisionLast revisionBoth sides next revision | ||
schedule [2021/12/16 16:10] – [Fall 2021 Lectures & Schedule] sjoao | schedule [2022/01/07 14:22] – rahbera | ||
---|---|---|---|
Line 40: | Line 40: | ||
| ::: | ::: | ::: | <hi #fff200> L15b: Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks </hi> \\ {{mensa__comparch__fall2021.pdf|(PDF)}} {{mensa__comparch__fall2021.pptx|(PPT)}} {{https:// | | ::: | ::: | ::: | <hi #fff200> L15b: Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks </hi> \\ {{mensa__comparch__fall2021.pdf|(PDF)}} {{mensa__comparch__fall2021.pptx|(PPT)}} {{https:// | ||
| ::: | ::: | ::: | <hi #fff200> L15c: CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations </hi> \\ {{codic-full-v1.1.pdf|(PDF)}} {{codic-full-v1.1.pptx|(PPT)}} {{https:// | | ::: | ::: | ::: | <hi #fff200> L15c: CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations </hi> \\ {{codic-full-v1.1.pdf|(PDF)}} {{codic-full-v1.1.pptx|(PPT)}} {{https:// | ||
- | | ::: | ::: | ::: | <hi #fff200> L15d: QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips </hi> \\ {{comparch-quac-trng.pdf|(PDF)}} {{comparch-quac-trng.pptx|(PPT)}} {{https:// | + | | ::: | 19.11 \\ Fri. | {{youtube> |
- | | ::: | 19.11 \\ Fri. | {{youtube> | + | | ::: | ::: | ::: | <hi #fff200> L16b: A Deeper Look into RowHammer’s Sensitivities: |
- | | ::: | ::: | ::: | <hi #fff200> L16b: A Deeper Look into RowHammer’s Sensitivities: | + | | ::: | ::: | ::: | <hi #fff200> L16c: BlockHammer: |
- | | ::: | ::: | ::: | <hi #fff200> L16c: BlockHammer: | + | | ::: | ::: | ::: | <hi #fff200> L16d: HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes </hi> \\ {{minesh_harp_lecture.pdf|(PDF)}} {{minesh_harp_lecture.pptx|(PPT)}} {{https:// |
- | | ::: | ::: | ::: | <hi #fff200> L16d: HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes </hi> \\ {{minesh_harp_lecture.pdf|(PDF)}} {{minesh_harp_lecture.pptx|(PPT)}} {{https:// | + | |
| W9 | 22.11 \\ Mon. | {{youtube> | | W9 | 22.11 \\ Mon. | {{youtube> | ||
| ::: | 25.11 \\ Thu. | {{youtube> | | ::: | 25.11 \\ Thu. | {{youtube> | ||
Line 57: | Line 56: | ||
| ::: | 10.12 \\ Fri. | {{youtube> | | ::: | 10.12 \\ Fri. | {{youtube> | ||
| W12 | 16.12 \\ Thu. | {{youtube> | | W12 | 16.12 \\ Thu. | {{youtube> | ||
- | and GPUs </hi> \\ {{onur-comparch-fall2021-lecture23-simd-and-gpu-afterlecture.pdf|(PDF)}} | + | and GPUs </hi> \\ {{onur-comparch-fall2021-lecture23-simd-and-gpu-afterlecture.pdf|(PDF)}} |
| ::: | 17.12 \\ Fri. | | <hi #fff200> Final Exam </hi> | | | | | | ::: | 17.12 \\ Fri. | | <hi #fff200> Final Exam </hi> | | | | | ||
+ | | W13 | 23.12 \\ Thu. | {{youtube> | ||
+ | | ::: | ::: | ::: | <hi #fff200> L24b: SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures </hi> \\ {{SynCron-HPCA2021_Cutting-edge_Lecture24_23_12_2021_clean.pdf|(PDF)}} {{SynCron-HPCA2021_Cutting-edge_Lecture24_23_12_2021_clean.pptx|(PPT)}} {{https:// | ||
+ | | ::: | ::: | ::: | <hi #fff200> L24c: SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM </hi> \\ {{simdram_comparch_fall21.pdf|(PDF)}} {{simdram_comparch_fall21.pptx|(PPT)}} {{https:// | ||
+ | | ::: | ::: | ::: | <hi #fff200> L24d: NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling & FPGA-based Near-Memory Acceleration of Modern Data-Intensive Applications </hi> \\ {{2021.12.23_nero_ieee_micro.pdf|(PDF)}} {{2021.12.23_nero_ieee_micro.pptx |(PPT)}} {{https:// | ||
+ |
schedule.txt · Last modified: 2022/01/14 12:47 by mnika