tutorials
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tutorials [2019/09/10 13:45] – external edit 127.0.0.1 | tutorials [2021/10/04 19:31] (current) – [Verilog Tutorials] sjoao | ||
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==== Verilog Tutorials ==== | ==== Verilog Tutorials ==== | ||
- | Combinational Logic, Hardware Description Lang. & Verilog | + | **Combinational Logic, Hardware Description Lang. & Verilog** |
- | Sequential Logic Design (Verilog tutorial begins on Slide 99) [Taken from Digitaltechnik Spring 2018] \\ {{onur-DigitalDesign-2018-lecture7-sequential-logic-afterlecture.pdf|(PDF)}} | + | * 2021 Digital Circuits, Lecture 7 \\ Starts in lecture slide 18: {{onur-digitaldesign_comparch-2021-lecture7-hdl-verilog-afterlecture.pdf | (PDF)}} {{onur-digitaldesign_comparch-2021-lecture7-hdl-verilog-afterlecture.pptx | (PPT)}} |
+ | * 2018 Digital Circuits, Lecture 6 \\ Starts in lecture slide 60: {{onur-digitaldesign-2018-lecture6-combinational-logic-hdl-verilog-afterlecture.pdf |(PDF)}} | ||
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+ | **Sequential Logic Design Using Verilog** | ||
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+ | * 2021 Digital Circuits, Lecture 7 \\ Starts in lecture slide 80: {{onur-digitaldesign_comparch-2021-lecture7-hdl-verilog-afterlecture.pdf | (PDF)}} {{onur-digitaldesign_comparch-2021-lecture7-hdl-verilog-afterlecture.pptx | (PPT)}} \\ Starts in video 1:30:33: https:// | ||
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+ | * 2018 Digital Circuits, Lecture 7 \\ Starts in lecture slide 99: {{onur-digitaldesign-2018-lecture7-sequential-logic-afterlecture.pdf | (PDF)}} | ||
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==== Vivado Tutorials ==== | ==== Vivado Tutorials ==== | ||
- | Basic tutorial for implementing an adder on your FPGA [Taken from Digitaltechnik Spring | + | Basic tutorial for implementing an adder on your FPGA [Taken from Digitaltechnik Spring |
tutorials.1568123114.txt.gz · Last modified: 2021/09/15 12:27 (external edit)