tutorials
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tutorials [2020/09/13 15:55] – [Vivado Tutorials] jispark | tutorials [2021/10/04 19:31] (current) – [Verilog Tutorials] sjoao | ||
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**Combinational Logic, Hardware Description Lang. & Verilog** | **Combinational Logic, Hardware Description Lang. & Verilog** | ||
- | * 2019 Digital Circuits, Lecture 7.2 \\ Starts in lecture, slide 9: {{onur-digitaldesign-2019-lecture7.2-hdl-afterlecture.pdf|(PDF)}} {{onur-digitaldesign-2019-lecture7.2-hdl-afterlecture.pptx| (PPT)}} \\ Starts in video 6:41: https:// | + | * 2021 Digital Circuits, Lecture 7 \\ Starts in lecture slide 18: {{onur-digitaldesign_comparch-2021-lecture7-hdl-verilog-afterlecture.pdf | (PDF)}} {{onur-digitaldesign_comparch-2021-lecture7-hdl-verilog-afterlecture.pptx | (PPT)}} \\ Starts in video 25:04: https:// |
- | * 2018 Digital Circuits, Lecture 6 \\ Starts in lecture, slide 60: {{onur-DigitalDesign-2018-lecture6-combinational-logic-HDL-verilog-afterlecture.pdf|(PDF)}} | + | * 2018 Digital Circuits, Lecture 6 \\ Starts in lecture slide 60: {{onur-digitaldesign-2018-lecture6-combinational-logic-hdl-verilog-afterlecture.pdf |(PDF)}} |
**Sequential Logic Design Using Verilog** | **Sequential Logic Design Using Verilog** | ||
- | * 2018 Digital Circuits, Lecture 7 \\ Starts in lecture, slide 99: {{onur-DigitalDesign-2018-lecture7-sequential-logic-afterlecture.pdf|(PDF)}} | + | * 2021 Digital Circuits, Lecture 7 \\ Starts in lecture |
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+ | * 2018 Digital Circuits, Lecture 7 \\ Starts in lecture | ||
==== Vivado Tutorials ==== | ==== Vivado Tutorials ==== | ||
- | Basic tutorial for implementing an adder on your FPGA [Taken from Digitaltechnik Spring | + | Basic tutorial for implementing an adder on your FPGA [Taken from Digitaltechnik Spring |
tutorials.1600012550.txt.gz · Last modified: 2021/09/15 12:27 (external edit)