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Seminar on Computer Architecture - Fall 2018
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papers
Papers
A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap with Expressive Memory
, ISCA 2018.
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks
, ASPLOS 2018.
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern DRAM Devices
, HPCA 2018.
Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology
, MICRO 2017.
Spectre Attacks: Exploiting Speculative Execution
, arxiv.org 2017.
GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping
, Bioinformatics 2017.
CLKSCREW: Exposing the Perils of Security-Oblivious Energy Management
, USENIX SECURITY 2017.
In-Datacenter Performance Analysis of a Tensor Processing Unit
, ISCA 2017.
Drammer: Deterministic Rowhammer Attacks on Mobile Platforms
, CCS 2016.
A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing
, ISCA 2015.
Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery
, HPCA 2015.
Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors
, ISCA 2014.
A reconfigurable fabric for accelerating large-scale datacenter services
, ISCA 2014.
Memory Persistency
, ISCA 2014.
Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory
, DSN 2014.
RAIDR: Retention-Aware Intelligent DRAM Refresh
, ISCA 2012.
MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP
, MICRO 2012.
Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches
, PACT 2012.
Improving GPU Performance via Large Warps and Two-Level Warp Scheduling
, MICRO 2011.
Dark silicon and the end of multicore scaling
, ISCA 2011.
CHIPPER: A Low-Complexity Bufferless Deflection Router
, HPCA 2011.
Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems
, ASPLOS 2010.
Understanding sources of inefficiency in general-purpose chips
, ISCA 2010.
Architecting Phase Change Memory as a Scalable DRAM Alternative
, ISCA 2009.
A Case for Bufferless Routing in On-Chip Networks
, ISCA 2009.
Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures
, ASPLOS 2009.
Self Optimizing Memory Controllers: A Reinforcement Learning Approach
, ISCA 2008.
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
, ISCA 2008.
Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems
, USENIX SECURITY 2007.
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
, MICRO 2006.
A Case for MLP-Aware Cache Replacement
, ISCA 2006.
Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors
, HPCA 2003.
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
, MICRO 2003.
Silicon Physical Random Functions
, CCS 2002.
Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution
, MICRO 2001.
Dynamic branch prediction with perceptrons
, HPCA 2001.
Slipstream processors: Improving both performance and fault tolerance
, ASPLOS 2000.
Simultaneous Subordinate Microthreading (SSMT)
, ISCA 1999.
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
, MICRO 1999.
The Case for a Single-Chip Multiprocessor
, ASPLOS 1996.
Multiscalar Processors
, ISCA 1995.
Transactional Memory: Architectural Support for Lock-Free Data Structures
, ISCA 1993.
Active Messages: A Mechanism for Integrating Computation and Communication
, ISCA 1992.
Why Systolic Architectures?
, IEEE Computer 1982.
papers.txt
· Last modified: 2019/02/12 17:35 (external edit)
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