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papers [2018/09/19 22:23]
hhasan created
papers [2019/02/12 17:35]
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-====== Papers ====== 
  
-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​X-MEM_Expressive-Memory-for-Rich-Cross-Layer-Abstractions_isca18.pdf|A Case for Richer Cross-layer Abstractions:​ Bridging the Semantic Gap with Expressive Memory]], ISCA 2018. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​Google-consumer-workloads-data-movement-and-PIM_asplos18.pdf|Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks]],​ ASPLOS 2018. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​dram-latency-puf_hpca18.pdf|The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern DRAM Devices]], HPCA 2018. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​ambit-bulk-bitwise-dram_micro17.pdf|Ambit:​ In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology]],​ MICRO 2017. 
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-  * {{spectre_attacks.pdf|Spectre Attacks: Exploiting Speculative Execution}},​ arxiv.org 2017. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​gatekeeper_FPGA-genome-prealignment-accelerator_bionformatics17.pdf|GateKeeper:​ A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping]], Bioinformatics 2017. 
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-  * {{clkscrew.pdf|CLKSCREW:​ Exposing the Perils of Security-Oblivious Energy Management}},​ USENIX SECURITY 2017.  
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-  * {{08192463.pdf|In-Datacenter Performance Analysis of a Tensor Processing Unit}}, ISCA 2017. 
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-  * {{drammer.pdf|Drammer:​ Deterministic Rowhammer Attacks on Mobile Platforms}},​ CCS 2016. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​tesseract-pim-architecture-for-graph-processing_isca15.pdf|A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]],​ ISCA 2015. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​flash-memory-data-retention_hpca15.pdf|Data Retention in MLC NAND Flash Memory: Characterization,​ Optimization and Recovery]], HPCA 2015. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​dram-row-hammer_isca14.pdf|Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors]], ISCA 2014. 
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-  * {{catapult.pdf|A reconfigurable fabric for accelerating large-scale datacenter services}}, ISCA 2014. 
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-  * {{mem_persistency.pdf|Memory Persistency}},​ ISCA 2014. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​heterogeneous-reliability-memory-for-data-centers_dsn14.pdf|Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory]], DSN 2014. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​raidr-dram-refresh_isca12.pdf|RAIDR:​ Retention-Aware Intelligent DRAM Refresh]], ISCA 2012. 
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-  * {{morphcore.pdf|MorphCore:​ An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP}}, MICRO 2012. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​bdi-compression_pact12.pdf|Base-Delta-Immediate Compression:​ Practical Data Compression for On-Chip Caches]], PACT 2012. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​large-gpu-warps_micro11.pdf|Improving GPU Performance via Large Warps and Two-Level Warp Scheduling]],​ MICRO 2011. 
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-  * {{darksilicon.pdf|Dark silicon and the end of multicore scaling}}, ISCA 2011. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​chipper_hpca11.pdf|CHIPPER:​ A Low-Complexity Bufferless Deflection Router]], HPCA 2011. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​fst_asplos10.pdf|Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems]], ASPLOS 2010. 
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-  * {{10.1.1.708.3891.pdf|Understanding sources of inefficiency in general-purpose chips}}, ISCA 2010. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​pcm_isca09.pdf|Architecting Phase Change Memory as a Scalable DRAM Alternative]],​ ISCA 2009. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​bless_isca09.pdf|A Case for Bufferless Routing in On-Chip Networks]], ISCA 2009. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​acs_asplos09.pdf|Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures]],​ ASPLOS 2009. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​rlmc_isca08.pdf|Self Optimizing Memory Controllers:​ A Reinforcement Learning Approach]], ISCA 2008. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems]], ISCA 2008. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​mph_usenix_security07.pdf|Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems]], USENIX SECURITY 2007. 
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-  * {{quereshi-micro2006.pdf|Utility-Based Cache Partitioning:​ A Low-Overhead,​ High-Performance,​ Runtime Mechanism to Partition Shared Caches}}, MICRO 2006. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​qureshi_isca06.pdf|A Case for MLP-Aware Cache Replacement]],​ ISCA 2006. 
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-  * [[https://​people.inf.ethz.ch/​omutlu/​pub/​mutlu_hpca03.pdf|Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors]],​ HPCA 2003. 
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-  * {{10.1.1.331.8266.pdf|Razor:​ A Low-Power Pipeline Based on Circuit-Level Timing Speculation}},​ MICRO 2003. 
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-  * {{10.1.1.297.5196.pdf|Silicon Physical Random Functions}},​ CCS 2002. 
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-  * {{p294-rajwar.pdf|Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution}},​ MICRO 2001. 
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-  * {{perceptron_branch_predictor.pdf|Dynamic branch prediction with perceptrons}},​ HPCA 2001. 
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-  * {{10.1.1.36.8249.pdf|Slipstream processors: Improving both performance and fault tolerance}},​ ASPLOS 2000. 
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-  * {{ssmt.pdf|Simultaneous Subordinate Microthreading (SSMT)}}, ISCA 1999. 
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-  * {{diva99.pdf|DIVA:​ A Reliable Substrate for Deep Submicron Microarchitecture Design}}, MICRO 1999. 
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-  * {{single_chip_multiprocessor.pdf|The Case for a Single-Chip Multiprocessor}},​ ASPLOS 1996. 
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-  * {{10.1.1.20.8558.pdf|Multiscalar Processors}},​ ISCA 1995. 
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-  * {{00698569.pdf|Transactional Memory: Architectural Support for Lock-Free Data Structures}},​ ISCA 1993. 
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-  * {{10.1.1.71.8606.pdf|Active Messages: A Mechanism for Integrating Computation and Communication}},​ ISCA 1992. 
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-  * {{1982-kung-why-systolic-architecture.pdf|Why Systolic Architectures?​}},​ IEEE Computer 1982. 
papers.txt ยท Last modified: 2019/02/12 17:35 (external edit)