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+ | ~~NOCACHE~~ | ||
+ | ====== Papers ====== | ||
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+ | * {{spectre_attacks.pdf|Spectre Attacks: Exploiting Speculative Execution}}, | ||
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+ | * {{clkscrew.pdf|CLKSCREW: | ||
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+ | * {{08192463.pdf|In-Datacenter Performance Analysis of a Tensor Processing Unit}}, ISCA 2017. | ||
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+ | * {{drammer.pdf|Drammer: | ||
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+ | * {{catapult.pdf|A reconfigurable fabric for accelerating large-scale datacenter services}}, ISCA 2014. | ||
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+ | * {{mem_persistency.pdf|Memory Persistency}}, | ||
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+ | * {{morphcore.pdf|MorphCore: | ||
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+ | * {{darksilicon.pdf|Dark silicon and the end of multicore scaling}}, ISCA 2011. | ||
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+ | * {{https:// | ||
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+ | * {{10.1.1.708.3891.pdf|Understanding sources of inefficiency in general-purpose chips}}, ISCA 2010. | ||
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+ | * {{quereshi-micro2006.pdf|Utility-Based Cache Partitioning: | ||
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+ | * {{10.1.1.331.8266.pdf|Razor: | ||
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+ | * {{10.1.1.297.5196.pdf|Silicon Physical Random Functions}}, | ||
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+ | * {{p294-rajwar.pdf|Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution}}, | ||
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+ | * {{perceptron_branch_predictor.pdf|Dynamic branch prediction with perceptrons}}, | ||
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+ | * {{10.1.1.36.8249.pdf|Slipstream processors: Improving both performance and fault tolerance}}, | ||
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+ | * {{ssmt.pdf|Simultaneous Subordinate Microthreading (SSMT)}}, ISCA 1999. | ||
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+ | * {{diva99.pdf|DIVA: | ||
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+ | * {{single_chip_multiprocessor.pdf|The Case for a Single-Chip Multiprocessor}}, | ||
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+ | * {{10.1.1.20.8558.pdf|Multiscalar Processors}}, | ||
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+ | * {{00698569.pdf|Transactional Memory: Architectural Support for Lock-Free Data Structures}}, | ||
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+ | * {{10.1.1.71.8606.pdf|Active Messages: A Mechanism for Integrating Computation and Communication}}, | ||
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+ | * {{1982-kung-why-systolic-architecture.pdf|Why Systolic Architectures? |