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readings [2018/09/19 15:48] juangreadings [2019/02/12 16:35] (current) – external edit 127.0.0.1
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 === Suggested (lecture 1): === === Suggested (lecture 1): ===
    * {{gordon_moore_1965_article.pdf|G.E. Moore, "Cramming more components onto integrated circuits," Electronics magazine, 1965}}    * {{gordon_moore_1965_article.pdf|G.E. Moore, "Cramming more components onto integrated circuits," Electronics magazine, 1965}}
-   {{https://en.wikipedia.org/wiki/The_Structure_of_Scientific_Revolutions|T.S. Kuhn, "The Structure of Scientific Revolutions," 1962}} +   [[https://en.wikipedia.org/wiki/The_Structure_of_Scientific_Revolutions|T.S. Kuhn, "The Structure of Scientific Revolutions," 1962]] 
-   {{https://www.wiley.com/en-us/The+Art+of+Computer+Systems+Performance+Analysis%3A+Techniques+for+Experimental+Design%2C+Measurement%2C+Simulation%2C+and+Modeling-p-9780471503361|R. Jain, "The Art of Computer Systems Performance Analysis," 1991}}+   [[https://www.wiley.com/en-us/The+Art+of+Computer+Systems+Performance+Analysis%3A+Techniques+for+Experimental+Design%2C+Measurement%2C+Simulation%2C+and+Modeling-p-9780471503361|R. Jain, "The Art of Computer Systems Performance Analysis," 1991]]
    * {{https://people.inf.ethz.ch/omutlu/pub/memory-channel-partitioning-micro11.pdf|S.P. Muralidhara, L. Subramanian, O. Mutlu, M. Kandemir, T. Moscibroda, "Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning," MICRO 2011}}    * {{https://people.inf.ethz.ch/omutlu/pub/memory-channel-partitioning-micro11.pdf|S.P. Muralidhara, L. Subramanian, O. Mutlu, M. Kandemir, T. Moscibroda, "Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning," MICRO 2011}}
  
 +===== Lecture 2 (26.09 Wed.) =====
 +=== Suggested (lecture 2): ===
 +  * {{https://people.inf.ethz.ch/omutlu/pub/ambit-bulk-bitwise-dram_micro17.pdf|V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M.A. Kozuch, O. Mutlu, P.B. Gibbons, T.C. Mowry, “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” MICRO 2017}}
 +  * {{https://people.inf.ethz.ch/omutlu/pub/lisa-dram_hpca16.pdf|K. Chang, P. Nair, S. Ghose, D. Lee, M. Qureshi, O. Mutlu, “Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM,” HPCA 2016}}
 +  *{{https://people.inf.ethz.ch/omutlu/pub/rowclone_micro13.pdf|V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, M.A. Kozuch, P.B. Gibbons, T.C. Mowry, "RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization," MICRO 2013}}
 +  *{{https://people.inf.ethz.ch/omutlu/pub/parbs_isca08.pdf|O. Mutlu and T. Moscibroda, "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems,” ISCA 2008.}}
 +  * {{https://people.inf.ethz.ch/omutlu/pub/stfm_micro07.pdf|O. Mutlu and T. Moscibroda, "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors," MICRO 2007}}
readings.1537372111.txt.gz · Last modified: 2019/02/12 16:35 (external edit)