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schedule [2018/12/19 17:04] – [2018 Lectures/Schedule] juangschedule [2018/12/19 23:20] – [2018 Lectures/Schedule] juang
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 | ::: | ::: | <hi #fff200>S9. 3. {{https://people.inf.ethz.ch/omutlu/pub/X-MEM_Expressive-Memory-for-Rich-Cross-Layer-Abstractions_isca18.pdf|A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap with Expressive Memory,}} ISCA 2018.</hi> \\ {{Voinov_Xmem_2018.pptx|(PPT)}} {{Voinov_Xmem_2018.pdf|(PDF)}}|  | | | ::: | ::: | <hi #fff200>S9. 3. {{https://people.inf.ethz.ch/omutlu/pub/X-MEM_Expressive-Memory-for-Rich-Cross-Layer-Abstractions_isca18.pdf|A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap with Expressive Memory,}} ISCA 2018.</hi> \\ {{Voinov_Xmem_2018.pptx|(PPT)}} {{Voinov_Xmem_2018.pdf|(PDF)}}|  | |
 | @#CEECF5:W14 | @#CEECF5:19.12 \\ Wed. | @#CEECF5:<hi #fff200>S10. 1. {{https://people.inf.ethz.ch/omutlu/pub/acs_asplos09.pdf|Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures,}} ASPLOS 2009.</hi> \\ {{ACS.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:| | @#CEECF5:W14 | @#CEECF5:19.12 \\ Wed. | @#CEECF5:<hi #fff200>S10. 1. {{https://people.inf.ethz.ch/omutlu/pub/acs_asplos09.pdf|Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures,}} ASPLOS 2009.</hi> \\ {{ACS.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:|
-| ::: | ::: | @#CEECF5:<hi #fff200>S10. 2. {{https://people.inf.ethz.ch/omutlu/pub/pcm_isca09.pdf|Architecting Phase Change Memory as a Scalable DRAM Alternative,}} ISCA 2009.</hi> \\ {{Bachelor-Seminar-Dec-19-Koppula-PCM-Memory.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:|+| ::: | ::: | @#CEECF5:<hi #fff200>S10. 2. {{https://people.inf.ethz.ch/omutlu/pub/pcm_isca09.pdf|Architecting Phase Change Memory as a Scalable DRAM Alternative,}} ISCA 2009.</hi> \\ {{Bachelor-Seminar-Dec-19-Koppula-PCM-Memory.pptx|(PPT)}} {{Bachelor-Seminar-Dec-19-Koppula-PCM-Memory.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:|
schedule.txt · Last modified: 2019/02/12 16:35 by 127.0.0.1