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schedule [2018/12/20 00:20]
juang [2018 Lectures/Schedule]
schedule [2019/02/12 17:35]
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-~~NOCACHE~~ 
  
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-====== 2018 Lectures/​Schedule ====== 
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-^ Week ^ Date ^ Lecture ^ Readings ^ HW ^ 
-| W1  |  19.09 \\ Wed.  |<hi #fff200> M1. Introduction</​hi>​ \\ {{onur-bachelorsseminarincomparch-fall2018-meeting1-intro-afterlecture.pptx| (PPT)}} {{onur-bachelorsseminarincomparch-fall2018-meeting1-intro-afterlecture.pdf|(PDF)}} \\ {{youtube>​link:​Vhydn-RLYXk| Video}} | [[readings#​Suggested (lecture 1)| Suggested]]|[[homeworks#​Homework 0: Student Information (Due: 23.09)| HW 0 Out]]| 
-| @#​CEECF5:​W2 ​ |  @#​CEECF5:​26.09 \\ Wed.  | @#​CEECF5:<​hi #fff200> M2. Logistics and Examples </hi> \\ {{onur-bachelorsseminarincomparch-fall2018-meeting2-example-reviews-afterlecture.pptx|(PPT)}} {{onur-BachelorsSeminarInCompArch-Fall2018-meeting2-example-reviews-afterlecture.pdf|(PDF)}} {{youtube>​link:​w5VZXtbWwuk|Video}} | @#​CEECF5:​[[readings#​Suggested (lecture 2)| Suggested]]| @#CEECF5: | 
-| W5  |  17.10 \\ Wed.  |<hi #fff200> S1. 1. {{https://​people.inf.ethz.ch/​omutlu/​pub/​mph_usenix_security07.pdf|Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems,}} USENIX SECURITY 2007 </hi> \\ {{Memory Performance Attacks- Denial of Memory Service in Multi-Core Systems_final.pptx|(PPT)}} {{Memory Performance Attacks- Denial of Memory Service in Multi-Core Systems_final.pdf|(PDF)}} | | | 
-| :::  |  :::  |<hi #fff200> S1. 2. {{1982-kung-why-systolic-architecture.pdf|Why Systolic Architectures?,​}} IEEE Computer 1982 </hi> \\ {{Why_systolic_architectures.pptx|(PPT)}} {{Why_systolic_architectures.pdf|(PDF)}}| | | 
-| @#CEECF5:W6 | @#​CEECF5:​24.10 \\ Wed. | @#​CEECF5:<​hi #​fff200>​S2. 1. {{https://​people.inf.ethz.ch/​omutlu/​pub/​rlmc_isca08.pdf|Self Optimizing Memory Controllers:​ A Reinforcement Learning Approach,}} ISCA 2008.</​hi>​ \\ {{CompArchSem18_MarcoZeller_self_optimizing.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:| 
-| ::: | ::: | @#​CEECF5:<​hi #​fff200>​S2. 2. {{morphcore.pdf|MorphCore:​ An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP,}} MICRO 2012.</​hi>​ \\  {{Morphcore_presentation.pptx|(PPT)}} {{Morphcore_presentation.pdf|(PDF)}}| @#CEECF5: | @#CEECF5:| 
-| W7 | 31.10 \\ Wed. | <hi #fff200> S3.1. {{https://​people.inf.ethz.ch/​omutlu/​pub/​tesseract-pim-architecture-for-graph-processing_isca15.pdf|A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing,​}} ISCA 2015.</​hi>​ \\ {{Bringolf _slides.pptx|(PPT)}} {{Bringolf _slides.pdf|(PDF)}} | | | 
-| ::: | ::: | <hi #​fff200>​S3. 2. {{darksilicon.pdf|Dark silicon and the end of multicore scaling,}} ISCA 2011.</​hi>​ \\ {{dark_silicon_4.0.pptx|(PPT)}} {{dark_silicon_4.0.pdf|(PDF)}} | | | 
-| ::: | ::: | <hi #​fff200>​S3. 3. {{https://​people.inf.ethz.ch/​omutlu/​pub/​gatekeeper_FPGA-genome-prealignment-accelerator_bionformatics17.pdf|GateKeeper:​ A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping,}} Bioinformatics 2017.</​hi>​ \\ {{Gatekeeper_presentation.pptx|(PPT)}} {{Gatekeeper_presentation.pdf|(PDF)}} |  | | 
-| @#CEECF5:W8 | @#​CEECF5:​07.11 \\ Wed. | @#​CEECF5:<​hi #​fff200>​S4. 1. {{https://​people.inf.ethz.ch/​omutlu/​pub/​dram-row-hammer_isca14.pdf|Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors,}} ISCA 2014.</​hi>​ \\ {{flipping_bits_benelli.pptx|(PPT)}} {{flipping_bits_benelli.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:| 
-| ::: | ::: | @#​CEECF5:<​hi #​fff200>​S4. 2. {{drammer.pdf|Drammer:​ Deterministic Rowhammer Attacks on Mobile Platforms,​}} CCS 2016.</​hi>​ \\ {{Drammer_Deterministic_Rowhammer_Attacks_on_Mobile_Platforms.pptx|(PPT)}} {{Drammer_Deterministic_Rowhammer_Attacks_on_Mobile_Platforms.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:| 
-| ::: | ::: | @#​CEECF5:<​hi #​fff200>​S4. 3. {{https://​people.inf.ethz.ch/​omutlu/​pub/​flash-memory-data-retention_hpca15.pdf|Data Retention in MLC NAND Flash Memory: Characterization,​ Optimization and Recovery,}} HPCA 2015.</​hi>​ \\ {{data_retention_nicolaswicki.pptx|(PPT)}} {{data_retention_nicolaswicki.pdf|(PDF)}}| @#CEECF5: | @#CEECF5:| 
-| W9 | 14.11 \\ Wed. | <hi #​fff200>​S5. 1. {{https://​people.inf.ethz.ch/​omutlu/​pub/​bless_isca09.pdf|A Case for Bufferless Routing in On-Chip Networks,}} ISCA 2009.</​hi>​ \\ {{a_case_for_bufferless_routing_in_on-chip_networks.pptx|(PPT)}} {{a_case_for_bufferless_routing_in_on-chip_networks.pdf|(PDF)}} |  | | 
-| ::: | ::: | <hi #​fff200>​S5. 2. {{https://​people.inf.ethz.ch/​omutlu/​pub/​raidr-dram-refresh_isca12.pdf|RAIDR:​ Retention-Aware Intelligent DRAM Refresh,}} ISCA 2012.</​hi>​ \\ {{RAIDR_burkhard.pptx|(PPT)}} {{RAIDR_burkhard.pdf|(PDF)}} |  | | 
-| ::: | ::: | <hi #​fff200>​S5. 3. {{10.1.1.71.8606.pdf|Active Messages: A Mechanism for Integrating Computation and Communication,​}} ISCA 1992.</​hi>​ \\ {{Active_Messages.pptx|(PPT)}} {{Active_Messages.pdf|(PDF)}} |  | | 
-| @#​CEECF5:​W10 | @#​CEECF5:​21.11 \\ Wed. | @#​CEECF5:<​hi #​fff200>​S6. 1. {{00698569.pdf|Transactional Memory: Architectural Support for Lock-Free Data Structures,​}} ISCA 1993.</​hi>​ \\ {{silvan_mosberger_transactional.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:| 
-| ::: | ::: | @#​CEECF5:<​hi #​fff200>​S6. 2. {{10.1.1.36.8249.pdf|Slipstream processors: Improving both performance and fault tolerance,​}} ASPLOS 2000.</​hi>​ \\ {{slipstream_final.pptx|(PPT)}} {{slipstream_final.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:| 
-| ::: | ::: | @#​CEECF5:<​hi #​fff200>​S6. 3. {{https://​people.inf.ethz.ch/​omutlu/​pub/​mutlu_hpca03.pdf|Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors,​}} HPCA 2003.</​hi>​ \\ {{runahead_execution_niederer.pptx|(PPT)}} {{runahead_execution_niederer.pdf|(PDF)}}| @#CEECF5: | @#CEECF5:| 
-| W11 | 28.11 \\ Wed. | <hi #​fff200>​S7. 1. {{https://​people.inf.ethz.ch/​omutlu/​pub/​ambit-bulk-bitwise-dram_micro17.pdf|Ambit:​ In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,​}} MICRO 2017.</​hi>​ \\ {{ambit_slides.pdf|(PDF)}} |  | | 
-| ::: | ::: | <hi #​fff200>​S7. 2. {{catapult.pdf|A reconfigurable fabric for accelerating large-scale datacenter services,}} ISCA 2014.</​hi>​ \\ {{catapult_slides.pptx|(PPT)}} {{catapult_slides.pdf|(PDF)}} |  | | 
-| ::: | ::: | <hi #​fff200>​S7. 3. {{spectre_attacks.pdf|Spectre Attacks: Exploiting Speculative Execution,​}} arxiv.org 2017.</​hi>​ \\ {{spectre_slides.pptx|(PPT)}} {{spectre_slides.pdf|(PDF)}} |  | | 
-| @#​CEECF5:​W12 | @#​CEECF5:​05.12 \\ Wed. | @#​CEECF5:<​hi #​fff200>​S8. 1. {{https://​people.inf.ethz.ch/​omutlu/​pub/​bdi-compression_pact12.pdf|Base-Delta-Immediate Compression:​ Practical Data Compression for On-Chip Caches,}} PACT 2012.</​hi>​ \\ {{s8.1_base-delta-immediate-compression.pptx|(PPT)}} {{s8.1_base-delta-immediate-compression.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:| 
-| ::: | ::: | @#​CEECF5:<​hi #​fff200>​S8. 2. {{https://​people.inf.ethz.ch/​omutlu/​pub/​large-gpu-warps_micro11.pdf|Improving GPU Performance via Large Warps and Two-Level Warp Scheduling,​}} MICRO 2011.</​hi>​ \\ {{gpu_warps-ondrejcernin-final.pptx|(PPT)}} {{gpu_warps-ondrejcernin-final.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:| 
-| ::: | ::: | @#​CEECF5:<​hi #​fff200>​S8. 3. {{10.1.1.297.5196.pdf|Silicon Physical Random Functions,​}} CCS 2002.</​hi>​ \\ {{SPUF_presentation.pptx|(PPT)}} {{SPUF_PDF.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:| 
-| W13 | 12.12 \\ Wed. | <hi #​fff200>​S9. 1. {{meltdown.pdf|Meltdown:​ Reading Kernel Memory from User Space,}} 27th USENIX Security Symposium 2018.</​hi>​ \\ {{Du_Meltdown_2018.pptx|(PPT)}} {{Du_Meltdown_2018.pdf|(PDF)}}| ​ | | 
-| ::: | ::: | <hi #​fff200>​S9. 2. {{clkscrew.pdf|CLKSCREW:​ Exposing the Perils of Security-Oblivious Energy Management,​}} USENIX SECURITY 2017.</​hi>​ \\ {{CLKSCREW_DominicWeibel.pptx|(PPT)}} {{CLKSCREW_DominicWeibel.pdf|(PDF)}}| ​ | | 
-| ::: | ::: | <hi #​fff200>​S9. 3. {{https://​people.inf.ethz.ch/​omutlu/​pub/​X-MEM_Expressive-Memory-for-Rich-Cross-Layer-Abstractions_isca18.pdf|A Case for Richer Cross-layer Abstractions:​ Bridging the Semantic Gap with Expressive Memory,}} ISCA 2018.</​hi>​ \\ {{Voinov_Xmem_2018.pptx|(PPT)}} {{Voinov_Xmem_2018.pdf|(PDF)}}| ​ | | 
-| @#​CEECF5:​W14 | @#​CEECF5:​19.12 \\ Wed. | @#​CEECF5:<​hi #​fff200>​S10. 1. {{https://​people.inf.ethz.ch/​omutlu/​pub/​acs_asplos09.pdf|Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures,​}} ASPLOS 2009.</​hi>​ \\ {{ACS.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:| 
-| ::: | ::: | @#​CEECF5:<​hi #​fff200>​S10. 2. {{https://​people.inf.ethz.ch/​omutlu/​pub/​pcm_isca09.pdf|Architecting Phase Change Memory as a Scalable DRAM Alternative,​}} ISCA 2009.</​hi>​ \\ {{Bachelor-Seminar-Dec-19-Koppula-PCM-Memory.pptx|(PPT)}} {{Bachelor-Seminar-Dec-19-Koppula-PCM-Memory.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:| 
schedule.txt ยท Last modified: 2019/02/12 17:35 (external edit)