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schedule [2018/11/27 13:52] juangschedule [2019/02/12 16:35] (current) – external edit 127.0.0.1
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 | ::: | ::: | <hi #fff200>S5. 2. {{https://people.inf.ethz.ch/omutlu/pub/raidr-dram-refresh_isca12.pdf|RAIDR: Retention-Aware Intelligent DRAM Refresh,}} ISCA 2012.</hi> \\ {{RAIDR_burkhard.pptx|(PPT)}} {{RAIDR_burkhard.pdf|(PDF)}} |  | | | ::: | ::: | <hi #fff200>S5. 2. {{https://people.inf.ethz.ch/omutlu/pub/raidr-dram-refresh_isca12.pdf|RAIDR: Retention-Aware Intelligent DRAM Refresh,}} ISCA 2012.</hi> \\ {{RAIDR_burkhard.pptx|(PPT)}} {{RAIDR_burkhard.pdf|(PDF)}} |  | |
 | ::: | ::: | <hi #fff200>S5. 3. {{10.1.1.71.8606.pdf|Active Messages: A Mechanism for Integrating Computation and Communication,}} ISCA 1992.</hi> \\ {{Active_Messages.pptx|(PPT)}} {{Active_Messages.pdf|(PDF)}} |  | | | ::: | ::: | <hi #fff200>S5. 3. {{10.1.1.71.8606.pdf|Active Messages: A Mechanism for Integrating Computation and Communication,}} ISCA 1992.</hi> \\ {{Active_Messages.pptx|(PPT)}} {{Active_Messages.pdf|(PDF)}} |  | |
-| @#CEECF5:W10 | @#CEECF5:21.11 \\ Wed. | @#CEECF5:<hi #fff200>S6. 1. {{00698569.pdf|Transactional Memory: Architectural Support for Lock-Free Data Structures,}} ISCA 1993.</hi> \\ | @#CEECF5: | @#CEECF5:+| @#CEECF5:W10 | @#CEECF5:21.11 \\ Wed. | @#CEECF5:<hi #fff200>S6. 1. {{00698569.pdf|Transactional Memory: Architectural Support for Lock-Free Data Structures,}} ISCA 1993.</hi> \\ {{silvan_mosberger_transactional.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:
-| ::: | ::: | @#CEECF5:<hi #fff200>S6. 2. {{10.1.1.36.8249.pdf|Slipstream processors: Improving both performance and fault tolerance,}} ASPLOS 2000.</hi> \\ {{.pptx|(PPT)}} {{.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:|+| ::: | ::: | @#CEECF5:<hi #fff200>S6. 2. {{10.1.1.36.8249.pdf|Slipstream processors: Improving both performance and fault tolerance,}} ASPLOS 2000.</hi> \\ {{slipstream_final.pptx|(PPT)}} {{slipstream_final.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:|
 | ::: | ::: | @#CEECF5:<hi #fff200>S6. 3. {{https://people.inf.ethz.ch/omutlu/pub/mutlu_hpca03.pdf|Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors,}} HPCA 2003.</hi> \\ {{runahead_execution_niederer.pptx|(PPT)}} {{runahead_execution_niederer.pdf|(PDF)}}| @#CEECF5: | @#CEECF5:| | ::: | ::: | @#CEECF5:<hi #fff200>S6. 3. {{https://people.inf.ethz.ch/omutlu/pub/mutlu_hpca03.pdf|Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors,}} HPCA 2003.</hi> \\ {{runahead_execution_niederer.pptx|(PPT)}} {{runahead_execution_niederer.pdf|(PDF)}}| @#CEECF5: | @#CEECF5:|
-| W11 | 28.11 \\ Wed. | <hi #fff200>S7. 1. {{https://people.inf.ethz.ch/omutlu/pub/ambit-bulk-bitwise-dram_micro17.pdf|Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,}} MICRO 2017.</hi> \\ |  | | +| W11 | 28.11 \\ Wed. | <hi #fff200>S7. 1. {{https://people.inf.ethz.ch/omutlu/pub/ambit-bulk-bitwise-dram_micro17.pdf|Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,}} MICRO 2017.</hi> \\ {{ambit_slides.pdf|(PDF)}} |  | | 
-| ::: | ::: | <hi #fff200>S7. 2. {{catapult.pdf|A reconfigurable fabric for accelerating large-scale datacenter services,}} ISCA 2014.</hi> \\ |  | | +| ::: | ::: | <hi #fff200>S7. 2. {{catapult.pdf|A reconfigurable fabric for accelerating large-scale datacenter services,}} ISCA 2014.</hi> \\ {{catapult_slides.pptx|(PPT)}} {{catapult_slides.pdf|(PDF)}} |  | | 
-| ::: | ::: | <hi #fff200>S7. 3. {{spectre_attacks.pdf|Spectre Attacks: Exploiting Speculative Execution,}} arxiv.org 2017.</hi> \\ |  | | +| ::: | ::: | <hi #fff200>S7. 3. {{spectre_attacks.pdf|Spectre Attacks: Exploiting Speculative Execution,}} arxiv.org 2017.</hi> \\ {{spectre_slides.pptx|(PPT)}} {{spectre_slides.pdf|(PDF)}} |  | | 
-| @#CEECF5:W12 | @#CEECF5:05.12 \\ Wed. | @#CEECF5:<hi #fff200>S8. 1. {{https://people.inf.ethz.ch/omutlu/pub/bdi-compression_pact12.pdf|Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches,}} PACT 2012.</hi> \\ | @#CEECF5: | @#CEECF5:+| @#CEECF5:W12 | @#CEECF5:05.12 \\ Wed. | @#CEECF5:<hi #fff200>S8. 1. {{https://people.inf.ethz.ch/omutlu/pub/bdi-compression_pact12.pdf|Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches,}} PACT 2012.</hi> \\ {{s8.1_base-delta-immediate-compression.pptx|(PPT)}} {{s8.1_base-delta-immediate-compression.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:
-| ::: | ::: | @#CEECF5:<hi #fff200>S8. 2. {{https://people.inf.ethz.ch/omutlu/pub/large-gpu-warps_micro11.pdf|Improving GPU Performance via Large Warps and Two-Level Warp Scheduling,}} MICRO 2011.</hi> \\ | @#CEECF5: | @#CEECF5:+| ::: | ::: | @#CEECF5:<hi #fff200>S8. 2. {{https://people.inf.ethz.ch/omutlu/pub/large-gpu-warps_micro11.pdf|Improving GPU Performance via Large Warps and Two-Level Warp Scheduling,}} MICRO 2011.</hi> \\ {{gpu_warps-ondrejcernin-final.pptx|(PPT)}} {{gpu_warps-ondrejcernin-final.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:
-| ::: | ::: | @#CEECF5:<hi #fff200>S8. 3. {{10.1.1.297.5196.pdf|Silicon Physical Random Functions,}} CCS 2002.</hi> \\ | @#CEECF5: | @#CEECF5:+| ::: | ::: | @#CEECF5:<hi #fff200>S8. 3. {{10.1.1.297.5196.pdf|Silicon Physical Random Functions,}} CCS 2002.</hi> \\ {{SPUF_presentation.pptx|(PPT)}} {{SPUF_PDF.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:
-| W13 | 12.12 \\ Wed. | <hi #fff200>S9. 1. {{meltdown.pdf|Meltdown: Reading Kernel Memory from User Space,}} 27th USENIX Security Symposium 2018.</hi> \\ |  | | +| W13 | 12.12 \\ Wed. | <hi #fff200>S9. 1. {{meltdown.pdf|Meltdown: Reading Kernel Memory from User Space,}} 27th USENIX Security Symposium 2018.</hi> \\ {{Du_Meltdown_2018.pptx|(PPT)}} {{Du_Meltdown_2018.pdf|(PDF)}}|  | | 
-| ::: | ::: | <hi #fff200>S9. 2. {{clkscrew.pdf|CLKSCREW: Exposing the Perils of Security-Oblivious Energy Management,}} USENIX SECURITY 2017.</hi> \\ |  | | +| ::: | ::: | <hi #fff200>S9. 2. {{clkscrew.pdf|CLKSCREW: Exposing the Perils of Security-Oblivious Energy Management,}} USENIX SECURITY 2017.</hi> \\ {{CLKSCREW_DominicWeibel.pptx|(PPT)}} {{CLKSCREW_DominicWeibel.pdf|(PDF)}}|  | | 
-| ::: | ::: | <hi #fff200>S9. 3. {{https://people.inf.ethz.ch/omutlu/pub/X-MEM_Expressive-Memory-for-Rich-Cross-Layer-Abstractions_isca18.pdf|A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap with Expressive Memory,}} ISCA 2018.</hi> \\ |  | |+| ::: | ::: | <hi #fff200>S9. 3. {{https://people.inf.ethz.ch/omutlu/pub/X-MEM_Expressive-Memory-for-Rich-Cross-Layer-Abstractions_isca18.pdf|A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap with Expressive Memory,}} ISCA 2018.</hi> \\ {{Voinov_Xmem_2018.pptx|(PPT)}} {{Voinov_Xmem_2018.pdf|(PDF)}}|  | 
 +| @#CEECF5:W14 | @#CEECF5:19.12 \\ Wed. | @#CEECF5:<hi #fff200>S10. 1. {{https://people.inf.ethz.ch/omutlu/pub/acs_asplos09.pdf|Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures,}} ASPLOS 2009.</hi> \\ {{ACS.pptx|(PPT)}} {{ACS.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:
 +| ::: | ::: | @#CEECF5:<hi #fff200>S10. 2. {{https://people.inf.ethz.ch/omutlu/pub/pcm_isca09.pdf|Architecting Phase Change Memory as a Scalable DRAM Alternative,}} ISCA 2009.</hi> \\ {{Bachelor-Seminar-Dec-19-Koppula-PCM-Memory.pptx|(PPT)}} {{Bachelor-Seminar-Dec-19-Koppula-PCM-Memory.pdf|(PDF)}} | @#CEECF5: | @#CEECF5:|
schedule.1543326764.txt.gz · Last modified: 2019/02/12 16:35 (external edit)