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Seminar on Computer Architecture - Fall 2018
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Papers
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HWs
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Computer Architecture FS18: Course Webpage
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schedule
This is an old revision of the document!
2018 Lectures/Schedule
Week
Date
Lecture
Readings
HW
W1
19.09
Wed.
M1. Introduction
(PPT)
(PDF)
Video
Suggested
HW 0 Out
W2
26.09
Wed.
M2. Logistics and Examples
(PPT)
(PDF)
Video
Suggested
W5
17.10
Wed.
S1. 1.
Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems,
USENIX SECURITY 2007
(PPT)
(PDF)
S1. 2.
Why Systolic Architectures?,
IEEE Computer 1982
(PPT)
(PDF)
W6
24.10
Wed.
S2. 1.
Self Optimizing Memory Controllers: A Reinforcement Learning Approach,
ISCA 2008.
(PDF)
S2. 2.
MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP,
MICRO 2012.
(PPT)
(PDF)
W7
31.10
Wed.
S3.1.
A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing,
ISCA 2015.
(PPT)
(PDF)
S3. 2.
Dark silicon and the end of multicore scaling,
ISCA 2011.
(PPT)
(PDF)
S3. 3.
GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping,
Bioinformatics 2017.
(PPT)
(PDF)
W8
07.11
Wed.
S4. 1.
Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors,
ISCA 2014.
(PPT)
(PDF)
S4. 2.
Drammer: Deterministic Rowhammer Attacks on Mobile Platforms,
CCS 2016.
(PPT)
(PDF)
S4. 3.
Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery,
HPCA 2015.
(PPT)
(PDF)
W9
14.11
Wed.
S5. 1.
A Case for Bufferless Routing in On-Chip Networks,
ISCA 2009.
(PPT)
(PDF)
S5. 2.
RAIDR: Retention-Aware Intelligent DRAM Refresh,
ISCA 2012.
(PPT)
(PDF)
S5. 3.
Active Messages: A Mechanism for Integrating Computation and Communication,
ISCA 1992.
(PPT)
(PDF)
W10
21.11
Wed.
S6. 1.
Transactional Memory: Architectural Support for Lock-Free Data Structures,
ISCA 1993.
(PDF)
S6. 2.
Slipstream processors: Improving both performance and fault tolerance,
ASPLOS 2000.
(PPT)
(PDF)
S6. 3.
Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors,
HPCA 2003.
(PPT)
(PDF)
W11
28.11
Wed.
S7. 1.
Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,
MICRO 2017.
(PDF)
S7. 2.
A reconfigurable fabric for accelerating large-scale datacenter services,
ISCA 2014.
(PPT)
(PDF)
S7. 3.
Spectre Attacks: Exploiting Speculative Execution,
arxiv.org 2017.
(PPT)
(PDF)
W12
05.12
Wed.
S8. 1.
Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches,
PACT 2012.
(PPT)
(PDF)
S8. 2.
Improving GPU Performance via Large Warps and Two-Level Warp Scheduling,
MICRO 2011.
(PPT)
(PDF)
S8. 3.
Silicon Physical Random Functions,
CCS 2002.
(PPT)
(PDF)
W13
12.12
Wed.
S9. 1.
Meltdown: Reading Kernel Memory from User Space,
27th USENIX Security Symposium 2018.
(PPT)
(PDF)
S9. 2.
CLKSCREW: Exposing the Perils of Security-Oblivious Energy Management,
USENIX SECURITY 2017.
(PPT)
(PDF)
S9. 3.
A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap with Expressive Memory,
ISCA 2018.
(PPT)
(PDF)
W14
19.12
Wed.
S10. 1.
Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures,
ASPLOS 2009.
(PPT)
(PDF)
S10. 2.
Architecting Phase Change Memory as a Scalable DRAM Alternative,
ISCA 2009.
(PPT)
(PDF)
schedule.1545303346.txt.gz
· Last modified: 2019/02/12 16:35 (external edit)
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