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Course Logistics and Presentation Preparation

Please check the paper assignment below and remember the presentation date. Please start preparing to present your assigned paper. Presentations will start on October 17.

Each student will present one paper (maximum 25 minutes) and lead discussion+brainstorming+feedback (maximum 10 minutes).

  • Step 1: Read and analyze your paper thoroughly
  • Step 2: Discuss with anyone you wish + use any resources
  • Step 3: Prepare a draft presentation based on guidelines (Study Lecture 1 and 2 again for presentation guidelines)
  • Step 4: Meet mentor(s) and get feedback. Meetings are mandatory – you have to schedule them with your assigned mentor(s).
  • Step 5: Revise the presentation and delivery
  • Step 6: Meet mentor(s) again and get further feedback
  • Step 7: Revise the presentation and delivery
  • Step 8: Practice, practice, practice

Schedule of Paper Presentations

Last Name First Name Paper Mentor1 Mentor2 Session (Date) Order in Day
Ettinger Florian Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems, USENIX SECURITY 2007. Minesh Can S1 (17.10) 1
Gregorio Sven Why Systolic Architectures?, IEEE Computer 1982. Mohammed Can S1 (17.10) 2
Zeller Marco Self Optimizing Memory Controllers: A Reinforcement Learning Approach, ISCA 2008. Hasan Juan S2 (24.10) 1
Fluri Lukas MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP, MICRO 2012. Geraldo Can S2 (24.10) 2
Bringolf Mauro A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing, ISCA 2015. Geraldo Juan S3 (31.10) 1
Ott Philipp Dark silicon and the end of multicore scaling, ISCA 2011. Giray Geraldo S3 (31.10) 2
Dantas Pereira Nuno GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping, Bioinformatics 2017. Mohammed Jeremie S3 (31.10) 3
Benelli Allan Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, ISCA 2014. Jeremie Minesh S4 (07.11) 1
Meinen Manuel Drammer: Deterministic Rowhammer Attacks on Mobile Platforms, CCS 2016. Ivan Mohammed S4 (07.11) 2
Wicki Nicolas Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery, HPCA 2015. Giray Mohammed S4 (07.11) 3
Bokstaller Jonas A Case for Bufferless Routing in On-Chip Networks, ISCA 2009. Can Juan S5 (14.11) 1
Burkhard Robin RAIDR: Retention-Aware Intelligent DRAM Refresh, ISCA 2012. Minesh Jeremie S5 (14.11) 2
Starc Roberto Active Messages: A Mechanism for Integrating Computation and Communication, ISCA 1992. Geraldo Giray S5 (14.11) 3
Mosberger Silvan Transactional Memory: Architectural Support for Lock-Free Data Structures, ISCA 1993. Minesh Jeremie S6 (21.11) 1
Keller Michael Slipstream processors: Improving both performance and fault tolerance, ASPLOS 2000. Juan Mohammed S6 (21.11) 2
Niederer Silvan Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors, HPCA 2003. Hasan Minesh S6 (21.11) 3
Knüsel Moritz Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology, MICRO 2017. Juan Geraldo S7 (28.11) 1
Bisping Robin A reconfigurable fabric for accelerating large-scale datacenter services, ISCA 2014. Mohammed Giray S7 (28.11) 2
Arcuti Giuseppe Spectre Attacks: Exploiting Speculative Execution, arxiv.org 2017. Ivan Hasan S7 (28.11) 3
Bartholomä Marc-Philippe Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches, PACT 2012. Hasan Geraldo S8 (05.12) 1
Cernin Ondrej Improving GPU Performance via Large Warps and Two-Level Warp Scheduling, MICRO 2011. Juan Hasan S8 (05.12) 2
Schläfli Fabian Silicon Physical Random Functions, CCS 2002. Jeremie Giray S8 (05.12) 3
Du Yinwei Meltdown: Reading Kernel Memory from User Space, 27th USENIX Security Symposium 2018. Giray Minesh S9 (12.12) 1
Weibel Dominic CLKSCREW: Exposing the Perils of Security-Oblivious Energy Management, USENIX SECURITY 2017. Ivan Hasan S9 (12.12) 2
Voinov Philippe A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap with Expressive Memory, ISCA 2018. Can Jeremie S9 (12.12) 3
Lazier Lara Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures, ASPLOS 2009. Hasan Juan S10 (19.12) 1
KoppulaSkandaArchitecting Phase Change Memory as a Scalable DRAM Alternative, ISCA 2009. Minesh Mohammed S10 (19.12) 2
sessions.txt · Last modified: 2019/02/12 17:35 (external edit)