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 ^ Last Name ^ First Name ^ Paper ^ Mentor1 ^ Mentor2 ^ Session (Date) ^ Order in Day ^  ^ Last Name ^ First Name ^ Paper ^ Mentor1 ^ Mentor2 ^ Session (Date) ^ Order in Day ^ 
-| Ettinger | Florian | [[https://​people.inf.ethz.ch/​omutlu/​pub/​mph_usenix_security07.pdf|Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems]], USENIX SECURITY 2007. | Minesh | Can | S1 (17.10) | 1 | +| Ettinger | Florian | {{https://​people.inf.ethz.ch/​omutlu/​pub/​mph_usenix_security07.pdf|Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems}}, USENIX SECURITY 2007. | Minesh | Can | S1 (17.10) | 1 | 
-@#6495ed:Gregorio | Sven | {{1982-kung-why-systolic-architecture.pdf|Why Systolic Architectures?​}},​ IEEE Computer 1982. | Mohammed | CanF | S1 (17.10) | 2 | +| Gregorio | Sven | {{1982-kung-why-systolic-architecture.pdf|Why Systolic Architectures?​}},​ IEEE Computer 1982. | Mohammed | Can | S1 (17.10) | 2 | 
-| Zeller | Marco | [[https://​people.inf.ethz.ch/​omutlu/​pub/​rlmc_isca08.pdf|Self Optimizing Memory Controllers:​ A Reinforcement Learning Approach]], ISCA 2008. | Hasan | Juan | S2 (24.10) | 1 | +@#CEECF5:Zeller | @#CEECF5:Marco | @#CEECF5:{{https://​people.inf.ethz.ch/​omutlu/​pub/​rlmc_isca08.pdf|Self Optimizing Memory Controllers:​ A Reinforcement Learning Approach}}, ISCA 2008. | @#CEECF5:Hasan | @#CEECF5:Juan | @#CEECF5:S2 (24.10) | @#CEECF5:1 | 
-| Fluri | Lukas | {{morphcore.pdf|MorphCore:​ An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP}}, MICRO 2012. | Geraldo | CanF | S2 (24.10) | 2 | +@#CEECF5:Fluri | @#CEECF5:Lukas | @#CEECF5:{{morphcore.pdf|MorphCore:​ An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP}}, MICRO 2012. | @#CEECF5:Geraldo | @#​CEECF5:​Can ​@#CEECF5:S2 (24.10) | @#CEECF5:2 | 
-| Bringolf | Mauro | [[https://​people.inf.ethz.ch/​omutlu/​pub/​tesseract-pim-architecture-for-graph-processing_isca15.pdf|A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]], ISCA 2015. | Geraldo | Juan | S3 (31.10) | 1 |+| Bringolf | Mauro | {{https://​people.inf.ethz.ch/​omutlu/​pub/​tesseract-pim-architecture-for-graph-processing_isca15.pdf|A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing}}, ISCA 2015. | Geraldo | Juan | S3 (31.10) | 1 |
 | Ott | Philipp | {{darksilicon.pdf|Dark silicon and the end of multicore scaling}}, ISCA 2011. | Giray | Geraldo | S3 (31.10) | 2 | | Ott | Philipp | {{darksilicon.pdf|Dark silicon and the end of multicore scaling}}, ISCA 2011. | Giray | Geraldo | S3 (31.10) | 2 |
-| Dantas Pereira | Nuno | [[https://​people.inf.ethz.ch/​omutlu/​pub/​gatekeeper_FPGA-genome-prealignment-accelerator_bionformatics17.pdf|GateKeeper:​ A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping]], Bioinformatics 2017. | Mohammed | Jeremie | S3 (31.10) | 3 | +| Dantas Pereira | Nuno | {{https://​people.inf.ethz.ch/​omutlu/​pub/​gatekeeper_FPGA-genome-prealignment-accelerator_bionformatics17.pdf|GateKeeper:​ A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping}}, Bioinformatics 2017. | Mohammed | Jeremie | S3 (31.10) | 3 | 
-| Benelli | Allan | [[https://​people.inf.ethz.ch/​omutlu/​pub/​dram-row-hammer_isca14.pdf|Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors]], ISCA 2014. | Jeremie | Minesh | S4 (07.11) | 1 | +@#CEECF5:Benelli | @#CEECF5:Allan | @#CEECF5:{{https://​people.inf.ethz.ch/​omutlu/​pub/​dram-row-hammer_isca14.pdf|Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors}}, ISCA 2014. | @#CEECF5:Jeremie | @#CEECF5:Minesh | @#CEECF5:S4 (07.11) | @#CEECF5:1 | 
-| Meinen | Manuel | {{drammer.pdf|Drammer:​ Deterministic Rowhammer Attacks on Mobile Platforms}},​ CCS 2016. | Ivan | Mohammed | S4 (07.11) | 2 | +@#CEECF5:Meinen | @#CEECF5:Manuel | @#CEECF5:{{drammer.pdf|Drammer:​ Deterministic Rowhammer Attacks on Mobile Platforms}},​ CCS 2016. | @#CEECF5:Ivan | @#CEECF5:Mohammed | @#CEECF5:S4 (07.11) | @#CEECF5:2 | 
-| Wicki | Nicolas | [[https://​people.inf.ethz.ch/​omutlu/​pub/​flash-memory-data-retention_hpca15.pdf|Data Retention in MLC NAND Flash Memory: Characterization,​ Optimization and Recovery]], HPCA 2015. | Giray | Mohammed | S4 (07.11) | 3 | +@#CEECF5:Wicki | @#CEECF5:Nicolas | @#CEECF5:{{https://​people.inf.ethz.ch/​omutlu/​pub/​flash-memory-data-retention_hpca15.pdf|Data Retention in MLC NAND Flash Memory: Characterization,​ Optimization and Recovery}}, HPCA 2015. | @#CEECF5:Giray | @#CEECF5:Mohammed | @#CEECF5:S4 (07.11) | @#CEECF5:3 | 
-| Bokstaller | Jonas | [[https://​people.inf.ethz.ch/​omutlu/​pub/​bless_isca09.pdf|A Case for Bufferless Routing in On-Chip Networks]], ISCA 2009. | Can | Juan | S5 (14.11) | 1 | +| Bokstaller | Jonas | {{https://​people.inf.ethz.ch/​omutlu/​pub/​bless_isca09.pdf|A Case for Bufferless Routing in On-Chip Networks}}, ISCA 2009. | Can | Juan | S5 (14.11) | 1 | 
-| Burkhard | Robin | [[https://​people.inf.ethz.ch/​omutlu/​pub/​raidr-dram-refresh_isca12.pdf|RAIDR:​ Retention-Aware Intelligent DRAM Refresh]], ISCA 2012. | Minesh | Jeremie | S5 (14.11) | 2 |+| Burkhard | Robin | {{https://​people.inf.ethz.ch/​omutlu/​pub/​raidr-dram-refresh_isca12.pdf|RAIDR:​ Retention-Aware Intelligent DRAM Refresh}}, ISCA 2012. | Minesh | Jeremie | S5 (14.11) | 2 |
 | Starc | Roberto | {{10.1.1.71.8606.pdf|Active Messages: A Mechanism for Integrating Computation and Communication}},​ ISCA 1992. | Geraldo | Giray | S5 (14.11) | 3 | | Starc | Roberto | {{10.1.1.71.8606.pdf|Active Messages: A Mechanism for Integrating Computation and Communication}},​ ISCA 1992. | Geraldo | Giray | S5 (14.11) | 3 |
-| Mosberger | Silvan | {{00698569.pdf|Transactional Memory: Architectural Support for Lock-Free Data Structures}},​ ISCA 1993. | Minesh | Jeremie | S6 (21.11) | 1 | +@#CEECF5:Mosberger | @#CEECF5:Silvan | @#CEECF5:{{00698569.pdf|Transactional Memory: Architectural Support for Lock-Free Data Structures}},​ ISCA 1993. | @#CEECF5:Minesh | @#CEECF5:Jeremie | @#CEECF5:S6 (21.11) | @#CEECF5:1 | 
-| Keller | Michael | {{10.1.1.36.8249.pdf|Slipstream processors: Improving both performance and fault tolerance}},​ ASPLOS 2000. | Juan | Mohammed | S6 (21.11) | 2 | +@#CEECF5:Keller | @#CEECF5:Michael | @#CEECF5:{{10.1.1.36.8249.pdf|Slipstream processors: Improving both performance and fault tolerance}},​ ASPLOS 2000. | @#CEECF5:Juan | @#CEECF5:Mohammed | @#CEECF5:S6 (21.11) | @#CEECF5:2 | 
-| Niederer | Silvan | [[https://​people.inf.ethz.ch/​omutlu/​pub/​mutlu_hpca03.pdf|Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors]], HPCA 2003. | Hasan | Minesh | S6 (21.11) | 3 | +@#CEECF5:Niederer | @#CEECF5:Silvan | @#CEECF5:{{https://​people.inf.ethz.ch/​omutlu/​pub/​mutlu_hpca03.pdf|Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors}}, HPCA 2003. | @#CEECF5:Hasan | @#CEECF5:Minesh | @#CEECF5:S6 (21.11) | @#CEECF5:3 | 
-| Knüsel | Moritz | [[https://​people.inf.ethz.ch/​omutlu/​pub/​ambit-bulk-bitwise-dram_micro17.pdf|Ambit:​ In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology]], MICRO 2017. | Juan | Geraldo | S7 (28.11) | 1 |+| Knüsel | Moritz | {{https://​people.inf.ethz.ch/​omutlu/​pub/​ambit-bulk-bitwise-dram_micro17.pdf|Ambit:​ In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology}}, MICRO 2017. | Juan | Geraldo | S7 (28.11) | 1 |
 | Bisping | Robin | {{catapult.pdf|A reconfigurable fabric for accelerating large-scale datacenter services}}, ISCA 2014. | Mohammed | Giray | S7 (28.11) | 2 | | Bisping | Robin | {{catapult.pdf|A reconfigurable fabric for accelerating large-scale datacenter services}}, ISCA 2014. | Mohammed | Giray | S7 (28.11) | 2 |
 | Arcuti | Giuseppe | {{spectre_attacks.pdf|Spectre Attacks: Exploiting Speculative Execution}},​ arxiv.org 2017. | Ivan | Hasan | S7 (28.11) | 3 | | Arcuti | Giuseppe | {{spectre_attacks.pdf|Spectre Attacks: Exploiting Speculative Execution}},​ arxiv.org 2017. | Ivan | Hasan | S7 (28.11) | 3 |
-| Bartholomä | Marc-Philippe | [[https://​people.inf.ethz.ch/​omutlu/​pub/​bdi-compression_pact12.pdf|Base-Delta-Immediate Compression:​ Practical Data Compression for On-Chip Caches]], PACT 2012. | Hasan | Geraldo | S8 (05.12) | 1 | +@#CEECF5:Bartholomä | @#CEECF5:Marc-Philippe | @#CEECF5:{{https://​people.inf.ethz.ch/​omutlu/​pub/​bdi-compression_pact12.pdf|Base-Delta-Immediate Compression:​ Practical Data Compression for On-Chip Caches}}, PACT 2012. | @#CEECF5:Hasan | @#CEECF5:Geraldo | @#CEECF5:S8 (05.12) | @#CEECF5:1 | 
-| Cernin | Ondrej | [[https://​people.inf.ethz.ch/​omutlu/​pub/​large-gpu-warps_micro11.pdf|Improving GPU Performance via Large Warps and Two-Level Warp Scheduling]], MICRO 2011. | Juan | Hasan | S8 (05.12) | 2 | +@#CEECF5:Cernin | @#CEECF5:Ondrej | @#CEECF5:{{https://​people.inf.ethz.ch/​omutlu/​pub/​large-gpu-warps_micro11.pdf|Improving GPU Performance via Large Warps and Two-Level Warp Scheduling}}, MICRO 2011. | @#CEECF5:Juan | @#CEECF5:Hasan | @#CEECF5:S8 (05.12) | @#CEECF5:2 | 
-| Schläfli | Fabian | {{10.1.1.297.5196.pdf|Silicon Physical Random Functions}},​ CCS 2002. | Jeremie | Giray | S8 (05.12) | 3 |+@#CEECF5:Schläfli | @#CEECF5:Fabian | @#CEECF5:{{10.1.1.297.5196.pdf|Silicon Physical Random Functions}},​ CCS 2002. | @#CEECF5:Jeremie | @#CEECF5:Giray | @#CEECF5:S8 (05.12) | @#CEECF5:3 |
 | Du | Yinwei | {{meltdown.pdf|Meltdown:​ Reading Kernel Memory from User Space}}, 27th USENIX Security Symposium 2018. | Giray | Minesh | S9 (12.12) | 1 | | Du | Yinwei | {{meltdown.pdf|Meltdown:​ Reading Kernel Memory from User Space}}, 27th USENIX Security Symposium 2018. | Giray | Minesh | S9 (12.12) | 1 |
 | Weibel | Dominic | {{clkscrew.pdf|CLKSCREW:​ Exposing the Perils of Security-Oblivious Energy Management}},​ USENIX SECURITY 2017.  | Ivan | Hasan | S9 (12.12) | 2 | | Weibel | Dominic | {{clkscrew.pdf|CLKSCREW:​ Exposing the Perils of Security-Oblivious Energy Management}},​ USENIX SECURITY 2017.  | Ivan | Hasan | S9 (12.12) | 2 |
-| Voinov | Philippe | [[https://​people.inf.ethz.ch/​omutlu/​pub/​X-MEM_Expressive-Memory-for-Rich-Cross-Layer-Abstractions_isca18.pdf|A Case for Richer Cross-layer Abstractions:​ Bridging the Semantic Gap with Expressive Memory]], ISCA 2018. | Can | Jeremie | S9 (12.12) | 3 |+| Voinov | Philippe | {{https://​people.inf.ethz.ch/​omutlu/​pub/​X-MEM_Expressive-Memory-for-Rich-Cross-Layer-Abstractions_isca18.pdf|A Case for Richer Cross-layer Abstractions:​ Bridging the Semantic Gap with Expressive Memory}}, ISCA 2018. | Can | Jeremie | S9 (12.12) | 3 
 +| @#​CEECF5:​Lazier | @#​CEECF5:​Lara | @#​CEECF5:​{{https://​people.inf.ethz.ch/​omutlu/​pub/​acs_asplos09.pdf|Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures}},​ ASPLOS 2009. | @#​CEECF5:​Hasan | @#​CEECF5:​Juan | @#​CEECF5:​S10 (19.12) | @#CEECF5:1 | 
 +| @#​CEECF5:​Koppula| @#​CEECF5:​Skanda| @#​CEECF5:​{{https://​people.inf.ethz.ch/​omutlu/​pub/​pcm_isca09.pdf|Architecting Phase Change Memory as a Scalable DRAM Alternative,​}} ISCA 2009. | @#​CEECF5:​Minesh | @#​CEECF5:​Mohammed | @#​CEECF5:​S10 (19.12) | @#​CEECF5:​2 ​|
sessions.1538563571.txt.gz · Last modified: 2019/02/12 17:35 (external edit)