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Seminar in Computer Architecture SS19: Course Webpage
Computer Architecture FS18: Course Webpage
Computer Architecture FS18: Lecture Videos
Design of Digital Circuits SS19: Course Webpage
Design of Digital Circuits SS19: Lecture Videos
readings
Table of Contents
Readings
Lecture 1 (19.09 Thu.)
Lecture 2 (26.09 Thu.)
Readings
Lecture 1 (19.09 Thu.)
Suggested (lecture 1):
G.E. Moore, "Cramming more components onto integrated circuits," Electronics magazine, 1965
T.S. Kuhn, "The Structure of Scientific Revolutions," 1962
R. Jain, "The Art of Computer Systems Performance Analysis," 1991
S.P. Muralidhara, L. Subramanian, O. Mutlu, M. Kandemir, T. Moscibroda, "Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning," MICRO 2011
Lecture 2 (26.09 Thu.)
Referenced Papers (lecture 2):
V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, M.A. Kozuch, P.B. Gibbons, T.C. Mowry, "RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization," MICRO, 2013.
S.P. Muralidhara, L. Subramanian, O. Mutlu, M. Kandemir, T. Moscibroda, “Reducing Memory Interference in Multicore Systems via Application-aware Memory Channel Partitioning,” MICRO 2011
M. Rosenblum, E. Bugnion, S.A. Herrod, E. Witchel, and A. Gupta, "The Impact of Architectural Trends on Operating System Performance,” In SIGOPS, 1995.
L. Zhao, R. Iyer, S. Makineni, L. Bhuyan, D. Newell, “Hardware Support for Bulk Data Movement in Server Platforms,” ICCD, 2005.
X. Jiang, Y. Solihin, L. Zhao, R. Iyer, “Architecture Support for Improving Bulk Memory Copying and Initialization Performance,” PACT, 2009
K. K. Chang, P. J. Nair, S. Ghose, D. Lee, M. K. Qureshi, O. Mutlu, "Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM", HPCA 2016
V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M.A. Kozuch, O. Mutlu, P.B. Gibbons, T.C. Mowry, “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” MICRO, 2017.
V. Seshadri, K. Hsieh, A. Boroumand, D. Lee, M.A. Kozuch, O.Mutlu, P.B. Gibbons, T.C. Mowry, "Fast Bulk Bitwise AND and OR in DRAM," IEEE CAL, 2015.
S Li, C Xu, Q Zou, J Zhao, Y Lu, Y Xie, "Pinatubo: A Processing-in-Memory Architecture for Bulk Bitwise Operations in Emerging Non-Volatile Memories," DAC, 2016
F. Gao, G. Tziantzioulis, D. Wentzlaff, "ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs," MICRO, 2019
W.K. Zuravleff and T. Robinson, “Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order” US Patent 5,630,096, May 1997.
Y. Kim, D. Han, O. Mutlu, M. Harchol-Balter, “ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers,” HPCA 2010
Y. Kim, M. Papamichel, O. Mutlu, M. Harchol-Balter, “Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior,” MICRO 2010
readings.txt
· Last modified: 2019/09/26 22:38 by
mpatel
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