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schedule [2019/12/17 12:43] alsermschedule [2021/04/14 14:12] (current) alserm
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 ===== Lecture Video Playlist on YouTube ===== ===== Lecture Video Playlist on YouTube =====
  
-[[https://www.youtube.com/playlist?list=PL5Q2soXY2Zi8OJwH_bn9UQqSF4wWYSzkp|Lecture Playlist]]+[[https://www.youtube.com/playlist?list=PL5Q2soXY2Zi_22a-Br3hXr55hy7s3ZDwH|Lecture Playlist]]
  
-{{url>https://www.youtube.com/embed/6yITVKTDV0s}}+{{url>https://www.youtube.com/embed?list=PL5Q2soXY2Zi_22a-Br3hXr55hy7s3ZDwH}}
  
 ====== 2019 Lectures/Schedule ====== ====== 2019 Lectures/Schedule ======
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 | W12  |  5.12 \\ Thu.  |<hi #fff200> S9.1: [[ https://people.inf.ethz.ch/omutlu/pub/drange-dram-latency-based-true-random-number-generator_hpca19.pdf | D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput ]], HPCA 2019</hi> \\ {{drange.pdf|(PDF)}} {{drange.ppt| (PPT)}}  | | | | W12  |  5.12 \\ Thu.  |<hi #fff200> S9.1: [[ https://people.inf.ethz.ch/omutlu/pub/drange-dram-latency-based-true-random-number-generator_hpca19.pdf | D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput ]], HPCA 2019</hi> \\ {{drange.pdf|(PDF)}} {{drange.ppt| (PPT)}}  | | |
 |  :::  |  :::  | <hi #fff200>S9.2: [[ https://people.inf.ethz.ch/omutlu/pub/bdi-compression_pact12.pdf | Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches ]], PACT 2012</hi> \\ {{ seminar_bdi_-_final_version.pdf |(PDF)}} {{seminar_bdi_-_final_version.pptx |(PPT)}}   | | | |  :::  |  :::  | <hi #fff200>S9.2: [[ https://people.inf.ethz.ch/omutlu/pub/bdi-compression_pact12.pdf | Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches ]], PACT 2012</hi> \\ {{ seminar_bdi_-_final_version.pdf |(PDF)}} {{seminar_bdi_-_final_version.pptx |(PPT)}}   | | |
-| W13  |  12.12 \\ Thu.  |<hi #fff200> S10.1: [[ http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.152.7595&rep=rep1&type=pdf | Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures ]], ASPLOS 2009</hi> \\ {{|(PDF)}} {{| (PPT)}}  | | | +| W13  |  12.12 \\ Thu.  |<hi #fff200> S10.1: [[ http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.152.7595&rep=rep1&type=pdf | Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures ]], ASPLOS 2009</hi> \\ {{accelerating_critical_section_execution_with_asymmetric_multi-core_architectures.pdf|(PDF)}} {{accelerating_critical_section_execution_with_asymmetric_multi-core_architectures.pptx| (PPT)}}  | | | 
-|  :::  |  :::  | <hi #fff200>S10.2: [[ https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8675237 | The Accelerator Wall: Limits of Chip Specialization ]], HPCA 2019</hi> \\ {{ |(PDF)}} {{ |(PPT)}}   | | |+|  :::  |  :::  | <hi #fff200>S10.2: [[ https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8675237 | The Accelerator Wall: Limits of Chip Specialization ]], HPCA 2019</hi> \\ {{comparchseminarpres_final.pdf |(PDF)}} {{comparchseminarpres.pptx |(PPT)}}   | | |
schedule.1576586596.txt.gz · Last modified: 2019/12/17 12:43 by alserm