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Course Logistics and Presentation Preparation

Please check the paper assignment below and remember the presentation date. Please start preparing to present your assigned paper. Presentations will start on Oct 10.

Each student will present and analyze one paper (maximum 30 minutes) and lead discussion+brainstorming+feedback (maximum 20 minutes).

  • Step 2: Check your assigned paper and presentation date.
  • Step 3: Contact your Mentor #1 and Mentor #2 to schedule a meeting.
  • Step 4: Read and analyze your paper thoroughly.
  • Step 5: Discuss with anyone you wish + use any resources.
  • Step 6: Prepare a draft presentation based on guidelines (Study Lecture 1 and 2 again for presentation guidelines).
  • Step 7: Meet mentors and get feedback. Meetings are mandatory – you have to schedule them with your assigned mentors.
  • Step 8: Revise the presentation and delivery.
  • Step 9: Meet mentors again and get further feedback.
  • Step 10: Revise the presentation and delivery.
  • Step 11: Practice, practice, practice.

Schedule of Paper Presentations

Last Name First Name Paper Mentor #1 Mentor #2 Session (Order in Day) Date
Gygi Lukas Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors , ISCA 2014 Giray Yaglikci Jawad Haj-Yahya S1.1 10-Oct
Mosler Maximilian Spectre Attacks: Exploiting Speculative Execution , IEEE Symposium on Security and Privacy 2019 Juan Gomez Luna Rahul Bera S1.2 10-Oct
Enderlin David Drammer: Deterministic Rowhammer Attacks on Mobile Platforms , CCS 2016 Minesh Patel Hasan Hassan S2.1 17-Oct
Schildknecht Bastian A2: Analog malicious hardware , IEEE Symposium on Security and Privacy 2016 Geraldo De Oliveira Junior Nika Mansouri Ghiasi S2.2 17-Oct
Tröndle Sarah CLKSCREW: Exposing the Perils of Security-Oblivious Energy Management , USENIX SECURITY 2017 Jeremie Kim Konstantinos Kanellopoulos S3.1 24-Oct
Lazier Lara FlashGuard: Leveraging Intrinsic Flash Properties to Defend Against Encryption Ransomware , CCS 2017 Giray Yaglikci Jisung Park S3.2 24-Oct
Karim Sabria RAIDR: Retention-Aware Intelligent DRAM Refresh , ISCA 2012 Hasan Hassan Can Firtina S4.1 31-Oct
Kleine Jan Lest we remember: cold-boot attacks on encryption keys , 17th USENIX Security Symposium 2008 Minesh Patel Geraldo De Oliveira Junior S4.2 31-Oct
Lüthi Guy FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives , ISCA 2018 Jisung Park Konstantinos Kanellopoulos S5.1 7-Nov
Lüscher Rasmus Efficient digital neurons for large scale cortical architectures , ISCA 2014 Can Firtina Nika Mansouri Ghiasi S5.2 7-Nov
Widmer Marc Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology , MICRO 2017 Juan Gomez Luna Konstantinos Kanellopoulos S6.1 14-Nov
Zhang Guanyin Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks , ISCA 2018 Jisung Park Minesh Patel S6.2 14-Nov
Rumpf Maximilian-David GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping , Bioinformatics 2017 Mohammed Rahul Bera S7.1 21-Nov
Frey Alexander GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies , BMC Genomics 2018 Jeremie Kim Mohammed Alser S7.2 21-Nov
Yan Anlin Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems , USENIX SECURITY 2007 Lois Orosa Giray Yaglikci S8.1 28-Nov
Tockner Felix Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems , ASPLOS 2010 Can Firtina Jeremie Kim S8.2 28-Nov
Hässig Manuel D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput , HPCA 2019 Hasan Hassan Jawad Haj-Yahya S9.1 5-Dec
Hodel Cliff Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches , PACT 2012 Jawad Haj-Yahya Geraldo De Oliveira Junior S9.2 5-Dec
Schweri Luca Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures , ASPLOS 2009 Nika Mansouri Ghiasi Lois Orosa S10.1 12-Dec
Burger Manuel The Accelerator Wall: Limits of Chip Specialization , HPCA 2019 Rahul Bera Lois Orosa S10.2 12-Dec
sessions.txt · Last modified: 2019/10/11 21:41 (external edit)