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Readings

Lecture 1.a (17.09 Thu.)

Suggested (lecture 1.a):

Lecture 1.b (17.09 Thu.)

Suggested (lecture 1.b):

Lecture 3 (01.10 Thu.)

Suggested (lecture 3):

Lecture 5.a (15.10 Thu.)

Suggested (lecture 5.a):

Lecture 5.b (15.10 Thu.)

Suggested (lecture 5.b):

Lecture 6.a (22.10 Thu.)

Suggested (lecture 6.a):

Lecture 6.b (22.10 Thu.)

Suggested (lecture 6.b):

Lecture 7.a (29.10 Thu.)

Suggested (lecture 7.a):

Lecture 7.b (29.10 Thu.)

Suggested (lecture 7.b):

Lecture 9 (12.11 Thu.)

Suggested (lecture 9.a):

Suggested (lecture 9.b):

Lecture 10 (19.11 Thu.)

Suggested (lecture 10.a):

Suggested (lecture 10.b):

* V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, M.A. Kozuch, P.B. Gibbons, T.C. Mowry, "RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization," MICRO, 2013. * V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M.A. Kozuch, O. Mutlu, P.B. Gibbons, T.C. Mowry, “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” MICRO, 2017. * A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan, and O. Mutlu, "Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,” ASPLOS, 2018. * S. Ghose, A. Boroumand, J. S. Kim, J. Gomez-Luna, and O. Mutlu, "Processing-in-Memory: A Workload-Driven Perspective," IBM Journal of Research & Development, 2019 * H. Hassan, N. Vijaykumar, S. Khan, S. Ghose, K. Chang, G. Pekhimenko, D. Lee, O. Ergin, O. Mutlu, "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies," HPCA 2017 * K. K. Chang, P. J. Nair, S. Ghose, D. Lee, M. K. Qureshi, O. Mutlu, "Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM," HPCA 2016 * S. Angizi, J. Sun, W. Zhang, D. Fan, "AlignS: A processing-in-memory accelerator for DNA short read alignment leveraging SOT-MRAM," DAC 2019 * D. Fujiki, S. Mahlke, R. Das, "Duality cache for data parallel acceleration," ISCA 2019 * Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, and Onur Mutlu, "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM," ISCA 2012 * S. Li, D. Niu, K.T. Malladi, H. Zheng, B. Brennan, Y. Xie, "Drisa: A dram-based reconfigurable in-situ accelerator," MICRO 2017 * Q. Deng, L. Jiang, Y. Zhang, M. Zhang, J. Yang, "DrAcc: a DRAM based accelerator for accurate CNN inference," DAC 2018

readings.1605779614.txt.gz · Last modified: 2020/11/19 10:53 by juang