User Tools

Site Tools


sessions

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision
Previous revision
sessions [2020/02/23 14:38] alsermsessions [2020/12/17 11:21] (current) – [Schedule of Paper Presentations] juang
Line 1: Line 1:
 ~~NOCACHE~~ ~~NOCACHE~~
-====== Course Logistics and Presentation Preparation ======+====== Presentation Preparation and Sessions ======
  
-Please check the paper assignment below and remember the presentation date. Please start preparing to present your assigned paper. **We will announce when the presentations will start**.+Please check the paper assignment below and remember the presentation date. Please start preparing to present your assigned paper.
  
 **Each student will present and analyze one paper (maximum 30 minutes) and lead discussion+brainstorming+feedback (maximum 20 minutes).** **Each student will present and analyze one paper (maximum 30 minutes) and lead discussion+brainstorming+feedback (maximum 20 minutes).**
  
-  * Step 1: Check the Sessions page: https://safari.ethz.ch/architecture_seminar/spring2020/doku.php?id=sessions+Please use the following algorithm to prepare for your talk: 
 + 
 +  * Step 1: Check the Sessions page: https://safari.ethz.ch/architecture_seminar/fall2020/doku.php?id=sessions
   * Step 2: Check your assigned paper and presentation date.   * Step 2: Check your assigned paper and presentation date.
-  * Step 3: Contact your Mentor #1 and Mentor #2 to schedule a meeting.+  * Step 3: Contact your Mentor #1Mentor #2, and Mentor #3 (if applicable) to schedule a meeting (do it now).
   * Step 4: Read and analyze your paper thoroughly.   * Step 4: Read and analyze your paper thoroughly.
   * Step 5: Discuss with anyone you wish + use any resources.   * Step 5: Discuss with anyone you wish + use any resources.
Line 17: Line 19:
   * Step 10: Revise the presentation and delivery.   * Step 10: Revise the presentation and delivery.
   * Step 11: Practice, practice, practice.   * Step 11: Practice, practice, practice.
 +We look forward to you participating in an enjoyable seminar course this semester.
 +
 ====== Schedule of Paper Presentations ====== ====== Schedule of Paper Presentations ======
-TBD+ 
 + 
 +^ Last Name ^ First Name ^ Paper ^ Mentor #1 ^ Mentor #2 ^ Mentor #3 ^ Session (Order in Day) and Date ^  
 +| Schoellen | Felix | [[ https://pdfs.semanticscholar.org/66c3/661f86ca40fed69e683288b2106635fa5f37.pdf | Architecture of the IBM System/360, IBM Journal of Research and Development 1964. ]] | Geraldo Francisco De Oliveira Junior | Damla Senol Cali | | S1.1 \\ 15 Oct | 
 +| Becker | Olivier | [[ https://www.microsoft.com/en-us/research/wp-content/uploads/2016/02/ISCA2010.pdf | Aergia: Exploiting Packet Latency Slack in On-Chip Networks, ISCA, 2010 ]]  | Nika Mansouri Ghiasi | Kosta Stojiljkovic | | S1.2 \\ 15 Oct | 
 +| @#CEECF5: Vilums | @#CEECF5: Georgijs | @#CEECF5: [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/exe/fetch.php?media=morphcore.pdf | MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP, MICRO 2012. ]] | @#CEECF5: Jawad Haj-Yahya | @#CEECF5: Kosta Stojiljkovic | @#CEECF5: | @#CEECF5: S2.1 \\ 22 Oct | 
 +| @#CEECF5: Maisch | @#CEECF5: Leandra | @#CEECF5: [[ https://people.inf.ethz.ch/omutlu/pub/continuous-runahead-engine_micro16.pdf | Continuous Runahead: Transparent Hardware Acceleration for Memory Intensive Workloads, MICRO 2016 ]] | @#CEECF5: Minesh Hamenbhai Patel | @#CEECF5: Haiyu Mao | @#CEECF5: | @#CEECF5: S2.2 \\ 22Oct | 
 +| Weidmann | Theo | [[ https://people.inf.ethz.ch/omutlu/pub/hamm_isca09.pdf | Flexible Reference Counting-Based Hardware Acceleration for Garbage Collection, ISCA 2009 ]] | Geraldo Francisco De Oliveira Junior | Konstantinos Kanellopoulos | | S3.1 \\ 29 Oct | 
 +| Scholbe | Stefan | [[ https://people.inf.ethz.ch/omutlu/pub/VBI-virtual-block-interface_isca20.pdf | The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework, ISCA, 2020 ]] | Lois Orosa Nogueira | Jisung Park | Nastaran | S3.2 \\ 29 Oct | 
 +| @#CEECF5: Adatte | @#CEECF5: Quentin | @#CEECF5: [[ https://safari.ethz.ch/architecture_seminar/fall2020/lib/exe/fetch.php?media=05008902.pdf | A Logic-in-Memory Computer, IEEE Trans. Comput., 1970 ]] | @#CEECF5: Gagandeep Singh | @#CEECF5: Nika Mansouri Ghiasi | @#CEECF5: | @#CEECF5: S4.2 \\ 5 Nov | 
 +| Brechbühl | Jérome | [[ https://safari.ethz.ch/architecture_seminar/fall2020/lib/exe/fetch.php?media=01199334.pdf | Using Memory Errors to Attack a Virtual Machine, IEEE Symposium on Security and Privacy, 2003 ]] | Minesh Hamenbhai Patel | Rahul Bera | | S5.1 \\ 12 Nov | 
 +| Müller | Julian | [[ https://people.inf.ethz.ch/omutlu/pub/rowhammer-TRRespass_ieee_security_privacy20.pdf | TRRespass: Exploiting the Many Sides of Target Row Refresh, IEEE Symposium on Security and Privacy, 2020 ]] | Abdullah Giray Yaglikci | Hasan Hassan | | S5.2 \\ 12 Nov | 
 +| @#CEECF5: Schumacher | @#CEECF5: David | @#CEECF5: [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?tok=388edc&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fdrange-dram-latency-based-true-random-number-generator_hpca19.pdf | D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput, HPCA 2019. ]] | @#CEECF5: Jeremie Kim | @#CEECF5: Mohammed Alser | @#CEECF5: | @#CEECF5: S6.1 \\ 19 Nov | 
 +| @#CEECF5: Meier | @#CEECF5: Christopher | @#CEECF5: [[ https://parallel.princeton.edu/papers/micro19-gao.pdf | ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs, MICRO 2019 ]] | @#CEECF5: Juan Gomez Luna | @#CEECF5: Nastaran | @#CEECF5: | @#CEECF5: S6.2 \\ 19 Nov | 
 +| Loher | Timo | [[ https://arxiv.org/pdf/1805.03718.pdf | Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks, ISCA 2018. ]] | Jisung Park | João Dinis Ferreira | | S7.1 \\ 26 Nov | 
 +| Kleymann | David | [[ https://people.inf.ethz.ch/omutlu/pub/hwbugs_micro08.pdf | Online Design Bug Detection: RTL Analysis, Flexible Mechanisms, and Evaluation, MICRO, 2008 ]] | Rahul Bera | Haiyu Mao | Jeremie Kim | S7.2 \\ 26 Nov | 
 +| @#CEECF5: Esterhammer | @#CEECF5: Arno | @#CEECF5: [[ https://rambleed.com/docs/20190603-rambleed-web.pdf | RAMBleed: Reading Bits in Memory Without Accessing Them, IEEE Symposium on Security and Privacy, 2020. ]] | @#CEECF5: Hasan Hassan | @#CEECF5: Abdullah Giray Yaglikci | @#CEECF5: | @#CEECF5: S8.1 \\ 3 Dec | 
 +| @#CEECF5: Krattenmacher | @#CEECF5: Jascha | @#CEECF5: [[ https://web.eecs.umich.edu/~taustin/papers/OAKLAND16-a2attack.pdf | A2: Analog malicious hardware, IEEE Symposium on Security and Privacy, 2016. ]] | @#CEECF5: Lois Orosa Nogueira | @#CEECF5: Jawad Haj-Yahya | @#CEECF5: | @#CEECF5: S8.2 \\ 3 Dec | 
 +| Oberdörfer | Tobias | [[ https://people.inf.ethz.ch/omutlu/pub/shouji-genome-prealignment-filter_bionformatics19.pdf | Shouji: A Fast and Efficient Pre-Alignment Filter for Sequence Alignment, Bioinformatics 2019 ]] | Mohammed Alser | Can Firtina | | S9.1 \\ 10 Dec | 
 +| Xuan | Cheng | [[ https://www.iscaconf.org/isca2020/papers/466100a391.pdf | Hardware-Software Co-Design for Brain-Computer Interfaces, ISCA, 2020 ]] | Konstantinos Kanellopoulos | Gagandeep Singh | | S9.2 \\ 10 Dec | 
 +| @#CEECF5: Vitez | @#CEECF5: Victor | @#CEECF5: [[ https://safari.ethz.ch/architecture_seminar/fall2020/lib/exe/fetch.php?media=s41467-020-15190-3.pdf | A programmable chemical computer with memory and pattern recognition, Nature Communications, 2020 ]] | @#CEECF5: Can Firtina | @#CEECF5: João Dinis Ferreira | @#CEECF5: | @#CEECF5: S10.1 \\ 17 Dec | 
sessions.1582468683.txt.gz · Last modified: 2020/09/10 13:46 (external edit)