buzzwords
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buzzwords [2021/04/29 15:06] – [Session 3 (15.04 Thu.)] haimao | buzzwords [2021/11/12 08:44] (current) – [Session 2 (11.11 Thu.)] nalserr | ||
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Buzzwords are terms that are mentioned during lecture which are particularly important to understand thoroughly. This page tracks the buzzwords for each of the lectures and can be used as a reference for finding gaps in your understanding of course material. | Buzzwords are terms that are mentioned during lecture which are particularly important to understand thoroughly. This page tracks the buzzwords for each of the lectures and can be used as a reference for finding gaps in your understanding of course material. | ||
- | ===== Lecture 1 (25.02 Thu.) ===== | + | ===== Lecture 1 (23.09 Thu.) ===== |
* Computer Architecture | * Computer Architecture | ||
* The transformation hierarchy | * The transformation hierarchy | ||
Line 36: | Line 36: | ||
* Design constrains | * Design constrains | ||
- | ===== Lecture 2 (04.03 Thu.) ===== | + | ===== Lecture 2 (30.9 Thu.) ===== |
- | *Data Movement | + | |
- | *Processing in memory (PIM) | + | |
- | *In-memory computation/ | + | |
- | *Near-data processing (NDP) | + | |
- | *UPMEM Processing-in-DRAM Engine | + | |
- | *3D-stacked memory | + | |
- | *RowClone | + | |
- | *Gather/ | + | |
- | *Bulk data copy and initialization | + | |
- | *In-Memory copy | + | |
- | *Intra-subarray | + | |
- | *Inter-bank | + | |
- | *Memory as an accelerator | + | |
- | *Low-cost Inter-linked subarrays (LISA) | + | |
- | *Fine-Grained In-DRAM Copy (FIGARO) | + | |
- | *Network-On-Memory | + | |
- | *Bulk Bitwise in-DRAM Computation (Ambit) | + | |
- | *Intelligent Memory Device | + | |
- | *ComputeDRAM | + | |
- | *Dual Contact Cell | + | |
- | *New memory technologies | + | |
- | + | ||
- | ===== Lecture 4 (18.03 | + | |
*Bioinformatics | *Bioinformatics | ||
*Genome Analysis | *Genome Analysis | ||
Line 105: | Line 82: | ||
*UPMEM | *UPMEM | ||
- | ===== Session 1 (25.03 Thu.) ===== | + | ===== Lecture 3 (07.10 Thu.) ===== |
- | *Spectre | + | *Data Movement |
- | *Branches | + | *Processing in memory (PIM) |
- | *Misspeculation | + | *In-memory computation/ |
- | *Out-of-Order | + | *Near-data processing |
- | *Flush cache | + | *UPMEM Processing-in-DRAM Engine |
- | *Side-channel attack | + | *3D-stacked memory |
- | *Rowhammer | + | *RowClone |
- | *DRAM scaling | + | *Gather/ |
- | *Bloom filter | + | *Bulk data copy and initialization |
- | *Blockhammer | + | *In-Memory copy |
- | *Throttle | + | *Intra-subarray |
- | *Blacklisting | + | *Inter-bank |
- | + | *Memory as an accelerator | |
- | ===== Session 2 (10.04 Thu.) ===== | + | *Low-cost Inter-linked subarrays |
- | *True Random Number Generators (TRNGs) | + | *Fine-Grained In-DRAM Copy (FIGARO) |
- | *NIST tests | + | *Network-On-Memory |
- | *DRAM cell Activation failure | + | *Bulk Bitwise in-DRAM Computation (Ambit) |
- | *Entropy source | + | *Intelligent Memory Device |
- | *DRAM timing constraints | + | *ComputeDRAM |
- | *Startup values | + | *Dual Contact Cell |
- | *Data retention | + | *New memory technologies |
- | *Charge sharing | + | |
- | *Bit-serial operations | + | |
- | *Bit-parallel arithmetics | + | |
- | *DRAM subarray | + | |
- | + | ||
- | + | ||
- | ===== Session 3 (15.04 Thu.) ===== | + | |
- | *PageRank | + | |
- | *Spatial/ | + | |
- | *3D stacking | + | |
- | *PIM | + | |
- | *PEI | + | |
- | *Intrinsics | + | |
- | *Locality-aware | + | |
- | *Through-Silicon Via (TSV) | + | |
- | *Hybrid Memory Cube (HMC) | + | |
- | *PIM Computation Unit (PCU) | + | |
- | *PIM Management Unit (PMU) | + | |
- | *Atomicity | + | |
- | *Reader-writer lock | + | |
- | *Cache coherence | + | |
- | *Locality-aware execution | + | |
- | + | ||
- | ===== Session 4 (22.04 Thu.) ===== | + | |
- | *On-chip networks | + | |
- | *Chip router | + | |
- | *Buffer routing | + | |
- | *Bufferless routing | + | |
- | *Reroute | + | |
- | *Youngest flit | + | |
- | *Head flit | + | |
- | *Worm deflection | + | |
- | *Worm truncation | + | |
- | *Routing mechanism | + | |
- | *Homogeneous | + | |
- | *High propability | + | |
- | *Congestion control | + | |
- | *Network | + | |
- | *Prefetcher | + | |
- | *Data-indirect workloads | + | |
- | *Data indirection graph | + | |
- | *Indirect memory accesses | + | |
- | *Breadth-First Search | + | |
- | *Data-dependent loads | + | |
- | *Load-dependent branches | + | |
- | *Allocator calls | + | |
- | *Dependent loads | + | |
- | *Adjacent bounds | + | |
- | *No inbound edges | + | |
- | *Dedicated SRAM | + | |
- | *Prefetch Status Handling Registers | + | |
+ | ===== Session 2 (11.11 Thu.) ===== | ||
+ | === Session 2.1 === | ||
+ | * Profiling | ||
+ | * Warehouse-scale Computer (WSCs) | ||
+ | * Microarchitectural Bottlenecks | ||
+ | * software/ | ||
+ | * Datacenter | ||
+ | * Google-Wide-Profiling (GWP) | ||
+ | * Performance Monitoring Unit (PMU) | ||
+ | * Datacenter Tax | ||
+ | * Retiring | ||
+ | * Bad Speculation | ||
+ | * Front-end Bound | ||
+ | * Back-end Bound | ||
+ | * Memory Hierarchy | ||
+ | * Instruction Cache | ||
+ | * Data Cache | ||
+ | * Instruction Level Parallelism (ILP) | ||
+ | * Memory Bandwidth | ||
+ | * Simultaneous Multi-Threading (SMT) | ||
+ | === Session 2.2 === | ||
+ | * Inefficiency | ||
+ | * General-Purpose Chips | ||
+ | * Processor Pipeline | ||
+ | * Single Instruction Multiple Data (SIMD) | ||
+ | * Very Long Instruction Word (VLIW) | ||
+ | * H.264 Algorithm | ||
+ | * Memory-Bound | ||
+ | * Magic Instructions |
buzzwords.1619708818.txt.gz · Last modified: 2021/09/15 12:26 (external edit)