Please check the list of papers below and then enter your preferences on the paper you would like to present during the seminar using the following link:

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• A case for exploiting subarray-level parallelism (SALP) in DRAM, ISCA 2012.
• A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap with Expressive Memory, ISCA 2018.
• A case for toggle-aware compression for GPU systems, HPCA 2016
• A Logic-in-Memory Computer", IEEE Trans. Comput., 1970
• A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data Locality, MICRO 2000
• Accelerating Genome Analysis: A Primer on an Ongoing Journey, IEEE Micro, 2020
• Analog content-addressable memories with memristors, Nature Communications 2020
• Architecting Waferscale Processors - A GPU Case Study, HPCA 2019
• BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, HPCA 2021
• Bottleneck Identification and Scheduling in Multithreaded Applications, ASPLOS 2012.
• Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches, MICRO 2021
• CAPE: A Content-Addressable Processing Engine, HPCA 2021
• Cellular Logic-in-Memory Arrays, IEEE TC 1969
• Classifying Memory Access Patterns for Prefetching, ASPLOS, 2020
• Computer structures: What have we learned from the PDP-11?, ISCA 1976
• CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators
• DeepStore: In-Storage Acceleration for Intelligent Queries, MICRO 2019
• Designing Vertical Processors in Monolithic 3D, ISCA 2019
• Die Stacking (3D) Microarchitecture, MICRO 2006
• Drammer: Deterministic Rowhammer Attacks on Mobile Platforms, CCS 2016.
• Energy Efficiency Boost in the AI-Infused POWER10 Processor, ISCA 2021
• Error Characterization, Mitigation, and Recovery in Flash Memory Based Solid State Drives, Proc IEEE 2017
• Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems, ASPLOS 2010.
• GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis, MICRO 2020
• Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks, PACT 2021
• Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks, ASPLOS 2018.
• Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology, ISCA 2021
• HoloAR: On-the-Fly Optimization of 3D Holographic Processing for Augmented Reality, MICRO 2021
• HPS, a new microarchitecture: rationale and introduction, ACM SIGMICRO Newsletter 1985
• IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors, ISCA 2021
• ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars, ISCA 2016.
• Lest we remember: cold-boot attacks on encryption keys, 17th USENIX Security Symposium, 2008.
• Leveraging EM Side-Channel Information to Detect Rowhammer Attacks, IEEE Symposium on Security and Privacy, 2020
• Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM, HPCA 2016
• NDS: N-Dimensional Storage, MICRO 2021
• Neural Acceleration for General-Purpose Approximate Programs, MICRO, 2012
• Processing in memory: the Terasys massively parallel PIM array, Computer 1995
• Profiling a Warehouse-scale Computer, ISCA, 2015.
• Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning, MICRO 2021
• QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips, ISCA 2021
• Quantifying Server Memory Frequency Margin and Using It to Improve Performance in HPC Systems, ISCA 2021
• Quantifying the Design-Space Tradeoffs in Autonomous Drones, ASPLOS 2021
• RAMBleed: Reading Bits in Memory Without Accessing Them, IEEE Symposium on Security and Privacy, 2020.
• Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques, ISCA 2020.
• Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors, HPCA 2003.
• SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM, ASPLOS 2021
• SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations, MICRO 2019
• SquiggleFilter: An Accelerator for Portable Virus Detection, MICRO 2021
• SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures, HPCA 2021
• Ten Lessons From Three Generations Shaped Google's TPUv4i, ISCA 2021
• The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework, ISCA, 2020
• Transactional Memory: Architectural Support for Lock-Free Data Structures, ISCA 1993.
• TRRespass: Exploiting the Many Sides of Target Row Refresh, IEEE Symposium on Security and Privacy, 2020
• Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications, MICRO 2021, MICRO 2021
• Understanding sources of inefficiency in general-purpose chips, ISCA 2010.
• Using Memory Errors to Attack a Virtual Machine, IEEE Symposium on Security and Privacy, 2003
• Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches, MICRO 2006.
• Very Long Instruction Word Architectures and the ELI-512, ISCA 1983
• Voltage Emergency Prediction: Using Signatures to Reduce Operating Margins, HPCA 2009
• You and Your Research, Transcription of the Bell Communications Research Colloquium Seminar 1986
• Zorua: A Holistic Approach to Resource Virtualization in GPUs, MICRO 2016
• A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses, MICRO 2021