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readings [2021/10/08 12:51] – [Lecture 2 (30.09 Thu.)] firtinacreadings [2021/12/30 11:02] (current) alserm
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   * {{https://people.inf.ethz.ch/omutlu/pub/processing-in-memory_workload-driven-perspective_IBMjrd19.pdf|Saugata Ghose, Amirali Boroumand, Jeremie S. Kim, Juan Gomez-Luna, and Onur Mutlu, "Processing-in-Memory: A Workload-Driven Perspective," IBM Journal of Research & Development, 2019}}    * {{https://people.inf.ethz.ch/omutlu/pub/processing-in-memory_workload-driven-perspective_IBMjrd19.pdf|Saugata Ghose, Amirali Boroumand, Jeremie S. Kim, Juan Gomez-Luna, and Onur Mutlu, "Processing-in-Memory: A Workload-Driven Perspective," IBM Journal of Research & Development, 2019}} 
   * {{https://people.inf.ethz.ch/omutlu/pub/dram-row-hammer_isca14.pdf|Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu, ”Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors”, ISCA, 2014}}   * {{https://people.inf.ethz.ch/omutlu/pub/dram-row-hammer_isca14.pdf|Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu, ”Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors”, ISCA, 2014}}
-  * {{https://arxiv.org/pdf/1904.09724.pdf|O. Mutlu, J. S. Kim, RowHammer: A Retrospective," arXiv, 2019}}+  * {{https://arxiv.org/pdf/1904.09724.pdf|O. Mutlu, J. S. Kim, RowHammer: A Retrospective," IEEE TCAD, 2019}}
   * {{https://people.inf.ethz.ch/omutlu/pub/Revisiting-RowHammer_isca20.pdf | Jeremie S. Kim, Minesh Patel, A. Giray Yaglikci, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu, “Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques”, ISCA 2020}}   * {{https://people.inf.ethz.ch/omutlu/pub/Revisiting-RowHammer_isca20.pdf | Jeremie S. Kim, Minesh Patel, A. Giray Yaglikci, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu, “Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques”, ISCA 2020}}
   * {{https://people.inf.ethz.ch/omutlu/pub/rowhammer-TRRespass_ieee_security_privacy20.pdf | Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi, "TRRespass: Exploiting the Many Sides of Target Row Refresh", Proceedings of the 41st IEEE Symposium on Security and. Privacy (S&P), 2020}}   * {{https://people.inf.ethz.ch/omutlu/pub/rowhammer-TRRespass_ieee_security_privacy20.pdf | Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi, "TRRespass: Exploiting the Many Sides of Target Row Refresh", Proceedings of the 41st IEEE Symposium on Security and. Privacy (S&P), 2020}}
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   * {{https://people.inf.ethz.ch/omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf| V. Seshadri, K. Hsieh, A. Boroumand, D. Lee, M.A. Kozuch, O.Mutlu, P.B. Gibbons, T.C. Mowry, "Fast Bulk Bitwise AND and OR in DRAM," IEEE CAL, 2015.}}   * {{https://people.inf.ethz.ch/omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf| V. Seshadri, K. Hsieh, A. Boroumand, D. Lee, M.A. Kozuch, O.Mutlu, P.B. Gibbons, T.C. Mowry, "Fast Bulk Bitwise AND and OR in DRAM," IEEE CAL, 2015.}}
   * {{https://cseweb.ucsd.edu/~jzhao/files/Pinatubo-dac2016.pdf|S. Li, C. Xu, Q. Zou, J. Zhao, Y. Lu, and Y. Xie, "Pinatubo: A Processing-in-Memory Architecture for Bulk Bitwise Operations in Emerging Non-volatile Memories," DAC, 2016}}   * {{https://cseweb.ucsd.edu/~jzhao/files/Pinatubo-dac2016.pdf|S. Li, C. Xu, Q. Zou, J. Zhao, Y. Lu, and Y. Xie, "Pinatubo: A Processing-in-Memory Architecture for Bulk Bitwise Operations in Emerging Non-volatile Memories," DAC, 2016}}
 +
 +===== Lecture 4 (14.10 Thu.) =====
 +
 +=== Suggested (lecture 4): ===
 +  * [[https://people.inf.ethz.ch/omutlu/pub/memory-channel-partitioning-micro11.pdf|Muralidhara, Sai Prashanth, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, and Thomas Moscibroda. "Reducing memory interference in multicore systems via application-aware memory channel partitioning." MICRO 2011.]]
 +  * {{https://people.inf.ethz.ch/omutlu/pub/tcm_ieee_micro_top_picks11.pdf|Yoongu Kim, Michael Papamichael, Onur Mutlu, and Mor Harchol-Balter, "Thread Cluster Memory Scheduling" MICRO 2011}}
 +  * {{https://people.inf.ethz.ch/omutlu/pub/atlas_hpca10.pdf|Yoongu Kim, Dongsu Han, Onur Mutlu, and Mor Harchol-Balter,"ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers" HPCA 2010}}
 +  * {{https://people.inf.ethz.ch/omutlu/pub/fst_asplos10.pdf|Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Patt,"Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems" ASPLOS 2010}}
 +  * {{https://people.inf.ethz.ch/omutlu/pub/application-to-core-mapping_hpca13.pdf|Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, and Mani Azimi,"Application-to-Core Mapping Policies to Reduce Memory System Interference in Multi-Core Systems" HPCA 2013}}
 +  * {{https://lph.ece.utexas.edu/merez/uploads/MattanErez/bpart_hpca12.pdf|Jeong, Min Kyu, Doe Hyun Yoon, Dam Sunwoo, Mike Sullivan, Ikhwan Lee, and Mattan Erez. "Balancing DRAM locality and parallelism in shared memory CMP systems." HPCA 2012.}}
 +  * {{https://liulei-sys-inventor.github.io/files/pact140-liu-final.pdf|Liu, Lei, Zehan Cui, Mingjie Xing, Yungang Bao, Mingyu Chen, and Chengyong Wu. "A software memory partition approach for eliminating bank-level interference in multicore systems." PACT 2012}}
 +  * {{http://users.ece.cmu.edu/~omutlu/pub/bliss-memory-scheduler_iccd14.pdf|Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, and Onur Mutlu, "The Blacklisting Memory Scheduler: Achieving High Performance and Fairness at Low Cost", ICCD 2014}}
 +  * {{https://people.inf.ethz.ch/omutlu/pub/bliss-memory-scheduler_ieee-tpds16.pdf|Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, and Onur Mutlu, "BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling" arXiv.org version, April 2015}}
 +
 +===== Session 1 (04.11 Thu.) =====
 +
 +=== Mentioned (Session 1) ===
 +
 +  * {{https://people.inf.ethz.ch/omutlu/pub/acs_asplos09.pdf|M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, and Yale N. Patt. "Accelerating critical section execution with asymmetric multi-core architectures." ASPLOS 2009.}}
 +  * {{https://people.inf.ethz.ch/omutlu/pub/dm_isca10.pdf|M. Aater Suleman, Onur Mutlu, Jose A. Joao, Khubaib, and Yale N. Patt. "Data Marshaling for Multi-core Architectures." ISCA 2010.}}
 +  * {{https://people.inf.ethz.ch/omutlu/pub/utility-based-acceleration-acmp_isca13.pdf|Jose A. Joao, M. Aater Suleman, Onur Mutlu, and Yale N. Patt. "Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs." ISCA 2013.}}
 +  * {{larrabee-manycore-164179.pdf|Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, and Pat Hanrahan. "Larrabee: a many-core x86 architecture for visual computing." ACM Transactions on Graphics, 2008.}}
 +
 +===== Session 2 (11.11 Thu.) =====
 +=== Mentioned (Session 2.1) ===
 +  * {{https://www.microsoft.com/en-us/research/wp-content/uploads/2016/06/asplos12_clearing_the_clouds.pdf|Michael Ferdman, Almutaz Adileh, Onur Kocberber, Stavros Volos, Mohammad Alisafaee, Djordje Jevdjic, Cansu Kaynak, Adrian Daniel Popescu, Anastasia Ailamaki, and Babak Falsafi. "Clearing the Clouds: A Study of Emerging Scale-out Workloads on Modern Hardware." ASPLOS 2012.}}
 +  * {{https://web.stanford.edu/~kozyraki/publications/2010.serverinsights.ieeemicro.pdf|Christos Kozyrakis, Aman Kansal, Sriram Sankar, Kushagra Vaid. "Server Engineering Insights for Large-Scale Online Services." IEEE Micro 2010.}}
 +  * {{https://static.googleusercontent.com/media/research.google.com/en//archive/googlecluster-ieee.pdf|L.A. Barroso, J. Dean, U. Holzle. "Web search for a planet: The Google cluster architecture." IEEE Micro 2003.}}
 +  * {{https://sagark.org/assets/pubs/protoacc-micro2021-preprint.pdf|Sagar Karandikar, Chris Leary, Chris Kennelly, Jerry Zhao, Dinesh Parimi, Borivoje Nikolic, Krste Asanovic, Parthasarathy Ranganathan. "A Hardware Accelerator for Protocol Buffers." MICRO 2021.}}
 +  * {{https://www.gwern.net/docs/cs/2021-ranganathan.pdf|Parthasarathy Ranganathan et. al. "Warehouse-scale video acceleration: co-design and deployment in the wild." ASPLOS 2021.}}
 +  * {{https://www.usenix.org/system/files/osdi21-hunter.pdf|A.H. Hunter, Jane Street Capital; Chris Kennelly, Paul Turner, Darryl Gove,Tipp Moseley, and Parthasarathy Ranganathan. "Beyond malloc efficiency to fleet efficiency: a hugepage-aware memory allocator." ASPLOS 2021.}}
 +  * {{https://www.cs.purdue.edu/homes/csjgwang/cloudb/WSCMemoryASPLOS19.pdf|Andres Lagar-Cavilla, Junwhan Ahn, Suleiman Souhlal, Neha Agarwal, Radoslaw Burny,Shakeel Butt, Jichuan Chang, Ashwin Chaugule, Nan Deng, Junaid Shahid, Greg Thelen,Kamil Adam Yurtsever, Yu Zhao, and Parthasarathy Ranganathan. "Software-Defined Far Memory in Warehouse-Scale Computers." ASPLOS 2019.}}
 +
 +=== Mentioned (Session 2.2) ===
 +  * {{http://meseec.ce.rit.edu/eecc722-fall2006/papers/reconfigurable-computing/1/micro94.pdf|Rahul Razdan and Michael D. Smith. "A High-Performance Microarchitecture with Hardware-Programmable Functional Units." MICRO 1994.}}
 +
 +
 +===== Session 3 (18.11 Thu.) =====
 +=== Mentioned (Session 3.1) ===
 +  * {{https://people.inf.ethz.ch/omutlu/pub/Pythia-customizable-hardware-prefetcher-using-reinforcement-learning_micro21.pdf| Rahul Bera, Konstantinos Kanellopoulos, Anant Nori, Taha Shahroodi, Sreenivas 
 +Subramoney, and Onur Mutlu, "Pythia: A Customizable Hardware Prefetching Framework
 +Using Online Reinforcement Learning" MICRO, 2021.}}
 +
 +=== Mentioned (Session 3.2) ===
 +  * [[ https://safari.ethz.ch/architecture_seminar/fall2021/lib/exe/fetch.php?media=3466752.3480053.pdf | Stephen Pruett and Yale N. Patt, "Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches", MICRO 2021 ]]
 +  * {{https://people.inf.ethz.ch/omutlu/pub/mutlu_ieee_micro03.pdf| Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt,"Runahead Execution: An Alternative to Very Large Instruction
 +Windows for Out-of-order Processors" MICRO TOP PICKS, 2003.}}
 +  * {{https://people.inf.ethz.ch/omutlu/pub/mutlu_ieee_micro03.pdf| Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt,"Runahead Execution: An Alternative to Very Large Instruction
 +Windows for Out-of-order Processors" MICRO TOP PICKS, 2003.}}
 +  * {{https://people.inf.ethz.ch/omutlu/pub/continuous-runahead-engine_micro16.pdf| Milad Hashemi, Onur Mutlu, and Yale N. Patt, "Continuous Runahead: Transparent Hardware Acceleration for Memory Intensive Workloads," MICRO, 2016.}}
 +
 +
 +===== Session 4 (25.11 Thu.) =====
 +=== Mentioned (Session 4.1) ===
 +  * [[ https://people.eecs.berkeley.edu/~kubitron/courses/cs252-F00/handouts/papers/p263-fisher.pdf |Joseph A. Fisher, "Very Long Instruction Word Architectures and the ELI-512", ISCA1983]]
 +  * {{http://people.eecs.berkeley.edu/~kubitron/courses/cs252-S09/handouts/papers/TraceScheduling.pdf|Joseph A. Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction." IEEE TC 1981.}}
 +
 +=== Mentioned (Session 4.2) ===
 +   * {{https://people.inf.ethz.ch/omutlu/pub/X-MEM_Expressive-Memory-for-Rich-Cross-Layer-Abstractions_isca18.pdf| Nandita Vijaykumar, Abhilasha Jain, Diptesh Majumdar, Kevin Hsieh, Gennady Pekhimenko, Eiman Ebrahimi, Nastaran Hajinazar, Phillip B. Gibbons, Onur Mutlu, "A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap with Expressive Memory", ISCA 2018.}}
 +
 +===== Session 5 (2.12 Thu.) =====
 +=== Mentioned (Session 5.1) ===
 +  * [[ https://people.cs.vt.edu/xunj/publications/heap_lab_isca_2021.pdf | Da Zhang, Gagandeep Panwar, Jagadish B.Kotra, Nathan DeBardeleben, Sean Blanchard, Xun Jian, "Quantifying Server Memory Frequency Margin and Using It to Improve Performance in HPC Systems", ISCA 2021 ]]
 +
 +=== Mentioned (Session 5.2) ===
 +  * [[https://people.inf.ethz.ch/omutlu/pub/SIMDRAM_asplos21.pdf|Nastaran Hajinazar, Geraldo F. Oliveira, Sven Gregorio, Joao Dinis Ferreira, Nika Mansouri Ghiasi, Minesh Patel, Mohammed Alser, Saugata Ghose, Juan Gomez-Luna, and Onur Mutlu, "SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM". Proceedings of the 26th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Virtual, March-April 2021.]]
 +
 +===== Session 6 (9.12 Thu.) =====
 +=== Mentioned (Session 6.1) ===
 +  * {{https://people.inf.ethz.ch/omutlu/pub/rowhammer-TRRespass_ieee_security_privacy20.pdf | Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi, “TRRespass: Exploiting the Many Sides of Target Row Refresh”, S&P 2020}}
 +  * {{https://people.inf.ethz.ch/omutlu/pub/Revisiting-RowHammer_isca20.pdf | Jeremie S. Kim, Minesh Patel, A. Giray Yaglikci, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu, “Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques”, ISCA 2020}}
 +  * {{https://people.inf.ethz.ch/omutlu/pub/CROW-DRAM-substrate-for-performance-energy-reliability_isca19.pdf|H. Hassan, M. Patel, J. S. Kim, A. G. Yaglikci, N. Vijaykumar, N. Mansourighiasi, S. Ghose, O. Mutlu, "CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability," ISCA 2019}}
 +  * {{https://arxiv.org/pdf/1904.09724.pdf|O. Mutlu, J. S. Kim, RowHammer: A Retrospective," IEEE TCAD, 2019}}
 +
 +=== Mentioned (Session 6.2) ===
 +  * [[https://people.inf.ethz.ch/omutlu/pub/BlockHammer_preventing-DRAM-rowhammer-at-low-cost_hpca21.pdf|A. Giray Yaglikci, Minesh Patel, Jeremie S. Kim, Roknoddin Azizi, Ataberk Olgun, Lois Orosa, Hasan Hassan, Jisung Park, Konstantinos Kanellopoulos, Taha Shahroodi, Saugata Ghose, and Onur Mutlu, "BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows". Proceedings of the 27th International Symposium on High-Performance Computer Architecture (HPCA), Virtual, February-March 2021.]]
 +  * {{https://safari.ethz.ch/architecture/fall2021/lib/exe/fetch.php?media=kim-isca14.pdf|Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu, ”Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors”, ISCA, 2014}}
 +  * {{https://arxiv.org/pdf/1904.09724.pdf|O. Mutlu, J. S. Kim, RowHammer: A Retrospective," IEEE TCAD, 2019}}
 +
 +===== Session 7 (16.12 Thu.) =====
 +=== Mentioned (Session 7.1) ===
 +  * [[https://rambleed.com/docs/20190603-rambleed-web.pdf| Andrew Kwong, Daniel Genkin, Daniel Gruss, Yuval Yarom, "RAMBleed: Reading Bits in Memory Without Accessing Them", IEEE Symposium on Security and Privacy, 2020.]]
 +  * [[https://people.inf.ethz.ch/omutlu/pub/BlockHammer_preventing-DRAM-rowhammer-at-low-cost_hpca21.pdf|A. Giray Yaglikci, Minesh Patel, Jeremie S. Kim, Roknoddin Azizi, Ataberk Olgun, Lois Orosa, Hasan Hassan, Jisung Park, Konstantinos Kanellopoulos, Taha Shahroodi, Saugata Ghose, and Onur Mutlu, "BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows". Proceedings of the 27th International Symposium on High-Performance Computer Architecture (HPCA), Virtual, February-March 2021.]]
 +  * {{https://safari.ethz.ch/architecture/fall2021/lib/exe/fetch.php?media=kim-isca14.pdf|Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu, ”Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors”, ISCA, 2014}}
 +  * {{https://arxiv.org/pdf/1904.09724.pdf|O. Mutlu, J. S. Kim, RowHammer: A Retrospective," IEEE TCAD, 2019}}
 +=== Mentioned (Session 7.2) ===
 +  * {{https://safari.ethz.ch/architecture_seminar/fall2021/lib/exe/fetch.php?media=ga03.ieeesnp.pdf|Using Memory Errors to Attack a Virtual Machine, IEEE S&P 2003.}}
 +  * {{https://arxiv.org/pdf/1904.09724.pdf|O. Mutlu, J. S. Kim, RowHammer: A Retrospective," IEEE TCAD, 2019}}
 +
 +===== Session 8 (23.12 Thu.) =====
 +=== Mentioned (Session 8.1) ===
 +  * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/exe/fetch.php?media=drammer.pdf | Drammer: Deterministic Rowhammer Attacks on Mobile Platforms, CCS 2016. ]]
 +  * {{https://people.inf.ethz.ch/omutlu/pub/rowhammer-TRRespass_ieee_security_privacy20.pdf | Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi, “TRRespass: Exploiting the Many Sides of Target Row Refresh”, S&P 2020}}
 +  * [[ https://www.usenix.org/system/files/conference/usenixsecurity16/sec16_paper_razavi.pdf| Kaveh Razavi, Ben Gras, and Erik Bosman, Bart Preneel, Cristiano Giuffrida and Herbert Bos, "Flip Feng Shui : Hammering a Needle in the Software Stack", 25th USENIX Security Symposium, 2016]]
 +  * [[ https://security.googleblog.com/2021/05/introducing-half-double-new-hammering.html| Salman Qazi, Yoongu Kim, Nicolas Boichat, Eric Shiu & Mattias Nissler, "Introducing Half-Double: New Hammering Technique for DRAM RowHammer
 +Bug" ]]
 +  * {{https://arxiv.org/pdf/1904.09724.pdf|O. Mutlu, J. S. Kim, RowHammer: A Retrospective," IEEE TCAD, 2019}}
 +
 +=== Mentioned (Session 8.2) ===
 +  * [[ https://arxiv.org/pdf/2108.06610.pdf | SquiggleFilter: An Accelerator for Portable Virus Detection, MICRO 2021 ]]
 +  * [[ https://www.sciencedirect.com/science/article/pii/S0019995885800462?via%3Dihub| E. Ukkonen, "Algorithms for approximate string matching", Information and Control, 1985]]
 +  * {{https://safari.ethz.ch/architecture/fall2021/lib/exe/fetch.php?media=genasm-approximate-string-matching-framework-for-genome-analysis_micro20.pdf|Damla Senol Cali, Gurpreet S. Kalsi, Zulal Bingol, Can Firtina, Lavanya Subramanian, Jeremie S. Kim, Rachata Ausavarungnirun, Mohammed Alser, Juan Gomez-Luna, Amirali Boroumand, Anant Nori, Allison Scibisz, Sreenivas Subramoney, Can Alkan, Saugata Ghose, and Onur Mutlu, "GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis," MICRO, 2020}}
 +  * [[ https://www.nature.com/articles/s41587-020-0731-9| Sam Kovaka, Yunfan Fan, Bohan Ni, Winston Timp & Michael C. Schatz, "Targeted nanopore sequencing by real-time mapping of raw electrical signal with UNCALLED", Nature Biotechnology, 2021]]
 +
 +=== Mentioned (Session 8.3) ===
 +  * [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?tok=d2103c&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2FGoogle-consumer-workloads-data-movement-and-PIM_asplos18.pdf | Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks, ASPLOS 2018. ]]
 +  * {{https://people.inf.ethz.ch/omutlu/pub/DAMOV-Bottleneck-Analysis-and-DataMovement-Benchmarks_arxiv21.pdf| G. F. Oliveira, J. Gomez-Luna, L. Orosa, S. Ghose, N. Vijaykumar, I. Fernandez, M. Sadrosadati, and O. Mutlu, "DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks"," IEEE Access, 2021}}
 +
 +
 +
  
readings.1633697481.txt.gz · Last modified: 2021/10/08 12:51 by firtinac