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• A case for exploiting subarray-level parallelism (SALP) in DRAM, ISCA 2012.
• A Case for Intelligent RAM, MICRO 1997
• A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap with Expressive Memory, ISCA 2018.
• A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations, arXiv 2022
• A Logic-in-Memory Computer", IEEE Trans. Comput., 1970
• A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data Locality, MICRO 2000
• A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing, ISCA 2015.
• A Study of SSD Reliability in Large Scale Enterpise Storage Deployments, FAST 2020
• A VLIW architecture for a trace scheduling compiler, ASPLOS 1987
• Accelerated Seeding for Genome Sequence Alignment with Enumerated Radix Trees, ISCA 2021
• Accelerating Pointer Chasing in 3D-Stacked Memory: Challenges, Mechanisms, Evaluation, ICCD 2016.
• Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology, MICRO 2017.
• AMD Prefetch Attacks through Power and Time, USENIX Security Symposium 2022
• Amdahl's Law in the Multicore Era, Computer 2008
• An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration, DSN 2020
• Architecting Phase Change Memory as a Scalable DRAM Alternative, ISCA 2009.
• Automatically characterizing large scale program behavior, ASPLOS 2002
• Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture, arXiv 2021
• Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System, IEEE Access 2022
• BioHD: An Efficient Genome Sequence Search Platform Using HyperDimensional Memorization, ISCA 22
• BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, HPCA 2021
• Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches, MICRO 2021
• CAPE: A Content-Addressable Processing Engine, HPCA 2021
• CellIFT: Leveraging Cells for Scalable and Precise Dynamic Information Flow Tracking in RTL, USENIX Security Symposium 2022
• Cellular Logic-in-Memory Arrays, IEEE TC 1969
• CHIPPER: A Low-Complexity Bufferless Deflection Router, HPCA 2011.
• Classifying Memory Access Patterns for Prefetching, ASPLOS, 2020
• CLKSCREW: Exposing the Perils of Security-Oblivious Energy Management, USENIX SECURITY 2017.
• CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations, ISCA 2021
• ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs, MICRO 2019
• CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators
• Cryptographic Capability Computing MICRO 2021
• CSI:Rowhammer – Cryptographic Security and Integrity against Rowhammer, IEEE Security & Privacy 2023
• D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput, HPCA 2019.
• DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design, MICRO 1999.
• DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators, HPCA 2022
• Drammer: Deterministic Rowhammer Attacks on Mobile Platforms, CCS 2016.
• Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory, MICRO 2022
• Flexible Reference Counting-Based Hardware Acceleration for Garbage Collection, ISCA 2009
• FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives, ISCA 2018
• GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis, MICRO 2020
• GenPIP: In-Memory Acceleration of Genome Analysis via Tight Integration of Basecalling and Read Mapping, MICRO 2022
• GenStore: a high-performance in-storage processing system for genome sequence analysis, ASPLOS 2022
• Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks, PACT 2021
• Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks, ASPLOS 2018.
• GraphSSD: Graph Semantics Aware SSD, ISCA, 2019
• Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology, ISCA 2021
• Hardware-Software Co-Design for Brain-Computer Interfaces, ISCA 2020
• HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes, MICRO 2021
• Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction, MICRO 2022
• HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips, MICRO 2022
• Hydra: Enabling Low-Overhead Mitigation of Row-Hammer at Ultra-Low Thresholds via Hybrid Tracking, ISCA 2022
• IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors, ISCA 2021
• ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars, ISCA 2016.
• Lest we remember: cold-boot attacks on encryption keys, 17th USENIX Security Symposium, 2008.
• Leveraging EM Side-Channel Information to Detect Rowhammer Attacks, IEEE Symposium on Security and Privacy, 2020
• MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations, TACO 2021
• MOESI-prime: Preventing Coherence-Induced Hammering in Commodity Workloads, ISCA 2022
• Morpheus: Extending the Last Level Cache in GPU Systems with Idle GPU Cores' Resources, MICRO 2022
• Mosaic: A GPU Memory Manager with Application-Transparent Support for Multiple Page Sizes, MICRO 2017
• Multiscalar Processors, ISCA 1995.
• NDMiner: Accelerating Graph Pattern Mining Using Near Data Processing, ISCA 2022
• NDS: N-Dimensional Storage, MICRO 2021
• Near-Stream Computing: General and Transparent Near-Cache Acceleration, HPCA 2022
• Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory, ISCA, 2016
• Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems, ISCA 2008.
• PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM, TACO 2022
• pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables, MICRO 2022
• Polynesia: Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Co-Design, ICDE 2022
• Processing in memory: the Terasys massively parallel PIM array, Computer 1995
• Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning, MICRO 2021
• QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips, ISCA 2021
• Quantifying the Design-Space Tradeoffs in Autonomous Drones, ASPLOS 2021
• Random access in large-scale DNA data storage, Nature biotechnology, 2018
• Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors, HPCA 2003.
• SecNDP: Secure Near-Data Processing with Untrusted Memory, HPCA 2022
• SeGraM: A Universal Hardware Accelerator for Genomic Sequence-to-Graph and Sequence-to-Sequence Mapping, ISCA 2022
• Self Optimizing Memory Controllers: A Reinforcement Learning Approach, ISCA 2008.
• Sibyl: Adaptive and Extensible Data Placement in Hybrid Storage Systems Using Online Reinforcement Learning, ISCA 2022
• SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM, ASPLOS 2021
• SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems, MICRO 2021
• SmartSAGE: Training Large-scale Graph Neural Networks using In-Storage Processing Architectures, ISCA 2022
• SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations, MICRO 2019
• SneakySnake: A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs, Bioinformatics 2020
• SpecHammer: Combining Spectre and Rowhammer for New Speculative Attacks, SP 2022
• SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures, HPCA 2021
• The Case for a Single-Chip Multiprocessor, ASPLOS 1996.
• The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework, ISCA, 2020
• Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications, MICRO 2021
• Using Memory Errors to Attack a Virtual Machine, IEEE Symposium on Security and Privacy, 2003
• Vector Runahead, ISCA 2021
• Voltage Emergency Prediction: Using Signatures to Reduce Operating Margins, HPCA 2009
• You and Your Research, Transcription of the Bell Communications Research Colloquium Seminar 1986