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~~NOCACHE~~ | ~~NOCACHE~~ | ||
====== Papers ====== | ====== Papers ====== | ||
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+ | ===== Paper preferences (Due: 4 March 2019, 11:59 pm Zurich) ===== | ||
+ | Please check the list of papers below and then enter your preferences on the paper you would like to present during the seminar using the following link: | ||
+ | * [[https:// | ||
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+ | ===== Paper list ===== | ||
* {{https:// | * {{https:// | ||
+ | * {{https:// | ||
+ | * {{ https:// | ||
* {{https:// | * {{https:// | ||
+ | * {{ https:// | ||
* {{https:// | * {{https:// | ||
- | * [[bottleneck-identification-and-scheduling_asplos12.pdf| Bottleneck Identification and Scheduling in Multithreaded Applications]]. ASPLOS'12 | + | * {{https:// |
+ | * {{http:// | ||
* {{https:// | * {{https:// | ||
* {{https:// | * {{https:// | ||
* {{https:// | * {{https:// | ||
- | * {{https:// | + | |
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* {{diva99.pdf|DIVA: | * {{diva99.pdf|DIVA: | ||
* {{https:// | * {{https:// | ||
* {{perceptron_branch_predictor.pdf|Dynamic branch prediction with perceptrons}}, | * {{perceptron_branch_predictor.pdf|Dynamic branch prediction with perceptrons}}, | ||
+ | * {{ http:// | ||
* {{https:// | * {{https:// | ||
* {{https:// | * {{https:// | ||
+ | * {{https:// | ||
* {{https:// | * {{https:// | ||
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* {{https:// | * {{https:// | ||
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+ | * {{ https:// | ||
* {{08192463.pdf|In-Datacenter Performance Analysis of a Tensor Processing Unit}}, ISCA 2017. | * {{08192463.pdf|In-Datacenter Performance Analysis of a Tensor Processing Unit}}, ISCA 2017. | ||
- | * {{https:// | + | |
- | * {{profiling_a_warehouse-scale_computer.pdf| "Profiling a Warehouse-scale Computer," | + | * {{https:// |
+ | * {{https:// | ||
+ | * {{http:// | ||
+ | * {{ https:// | ||
+ | * {{https:// | ||
+ | < | ||
+ | * {{https:// | ||
+ | * {{ http:// | ||
+ | * {{https:// | ||
* {{https:// | * {{https:// | ||
+ | * {{https:// | ||
* {{https:// | * {{https:// | ||
- | * {{spectre_attacks.pdf|Spectre Attacks: Exploiting Speculative Execution}}, | + | * {{ https:// |
+ | * {{https:// | ||
* {{p294-rajwar.pdf|Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution}}, | * {{p294-rajwar.pdf|Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution}}, | ||
* {{single_chip_multiprocessor.pdf|The Case for a Single-Chip Multiprocessor}}, | * {{single_chip_multiprocessor.pdf|The Case for a Single-Chip Multiprocessor}}, | ||
+ | * {{https:// | ||
+ | * {{https:// | ||
* {{10.1.1.708.3891.pdf|Understanding sources of inefficiency in general-purpose chips}}, ISCA 2010. | * {{10.1.1.708.3891.pdf|Understanding sources of inefficiency in general-purpose chips}}, ISCA 2010. | ||
- | * {{https://people.inf.ethz.ch/omutlu/pub/qureshi_isca06.pdf|A Case for MLP-Aware Cache Replacement}}, | + | * {{https://www.cs.princeton.edu/~appel/papers/memerr.pdf | Using Memory Errors to Attack a Virtual Machine}}, IEEE Symposium on Security and Privacy 2003 |
- | * {{https:// | + | |
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papers.1550682340.txt.gz · Last modified: 2019/02/20 17:05 by alserm