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Papers

A Case for Bufferless Routing in On-Chip Networks, ISCA 2009.
A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing, ISCA 2015.
Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology, MICRO 2017.
Bottleneck Identification and Scheduling in Multithreaded Applications, ASPLOS 2012
Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory, DSN 2014.
Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory, DSN 2014.
CHIPPER: A Low-Complexity Bufferless Deflection Router, HPCA 2011.
Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding, ArXiv 2016.
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design, MICRO 1999.
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput", HPCA 2019.
Dynamic branch prediction with perceptrons, HPCA 2001.
Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems, ASPLOS 2010.
Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, ISCA 2014.
GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping, Bioinformatics 2017.
GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies, BMC Genomics, 2018
Focus: Querying Large Video Datasets with Low Latency and Low Cost, Proceedings of the 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI), 2018.
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks, ASPLOS 2018.
In-Datacenter Performance Analysis of a Tensor Processing Unit, ISCA 2017.
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems, ISCA 2008.
"Profiling a Warehouse-scale Computer," ISCA, 2015.
RAIDR: Retention-Aware Intelligent DRAM Refresh, ISCA 2012.
Self Optimizing Memory Controllers: A Reinforcement Learning Approach, ISCA 2008.
Spectre Attacks: Exploiting Speculative Execution, arxiv.org 2017.
Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution, MICRO 2001.
The Case for a Single-Chip Multiprocessor, ASPLOS 1996.
Understanding sources of inefficiency in general-purpose chips, ISCA 2010.
A Case for MLP-Aware Cache Replacement, ISCA 2006.
Architecting Phase Change Memory as a Scalable DRAM Alternative, ISCA 2009.
Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems, USENIX SECURITY 2007.
Mosaic: Enabling Application-Transparent Support for Multiple Page Sizes in Throughput Processors, ACM SIGOPS Operating Systems Review 2018.
"Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture," HPCA 2013
A Large Scale Study of Data Center Network Reliability, Proceedings of the 18th ACM Internet Measurement Conference (IMC) 2018.
Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management, ISCA 2015.
"PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture," ISCA, 2015.
"Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery", DSN, 2015
“Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior,” MICRO 2010
Using Memory Errors to Attack a Virtual Machine, IEEE Symposium on Security and Privacy 2003

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