User Tools

Site Tools


papers

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
papers [2019/02/20 18:06]
alserm
papers [2019/04/20 08:39] (current)
Line 1: Line 1:
 ~~NOCACHE~~ ~~NOCACHE~~
 ====== Papers ====== ====== Papers ======
 +
 +
 +===== Paper preferences (Due: 4 March 2019, 11:59 pm Zurich) =====
 +Please check the list of papers below and then enter your preferences on the paper you would like to present during the seminar using the following link:
 +  * [[https://​moodle-app2.let.ethz.ch/​mod/​ratingallocate/​view.php?​id=340139 | Submit your preferences]]
 +
 +
 +
 +===== Paper list =====
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​bless_isca09.pdf|A Case for Bufferless Routing in On-Chip Networks}}, ISCA 2009.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​bless_isca09.pdf|A Case for Bufferless Routing in On-Chip Networks}}, ISCA 2009.
 +  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​qureshi_isca06.pdf|A Case for MLP-Aware Cache Replacement}},​ ISCA 2006.
 +  * {{ https://​people.inf.ethz.ch/​omutlu/​pub/​data-center-network-errors-at-facebook_imc18.pdf | A Large Scale Study of Data Center Network Reliability}}, ​ ACM IMC 2018.
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​tesseract-pim-architecture-for-graph-processing_isca15.pdf|A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing}},​ ISCA 2015.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​tesseract-pim-architecture-for-graph-processing_isca15.pdf|A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing}},​ ISCA 2015.
 +  * {{ https://​ieeexplore.ieee.org/​iel7/​7528194/​7546461/​07546493.pdf |  A2: Analog malicious hardware}}, IEEE Symposium on Security and Privacy 2016.
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​ambit-bulk-bitwise-dram_micro17.pdf|Ambit:​ In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology}},​ MICRO 2017.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​ambit-bulk-bitwise-dram_micro17.pdf|Ambit:​ In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology}},​ MICRO 2017.
-  * {{bottleneck-identification-and-scheduling_asplos12.pdf | Bottleneck Identification and Scheduling in Multithreaded Applications}},​ ASPLOS 2012+  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​pcm_isca09.pdf|Architecting Phase Change Memory as a Scalable DRAM Alternative}},​ ISCA 2009. 
 +  * {{http://​users.ece.cmu.edu/​~omutlu/​pub/​bottleneck-identification-and-scheduling_asplos12.pdf | Bottleneck Identification and Scheduling in Multithreaded Applications}},​ ASPLOS 2012.
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​heterogeneous-reliability-memory-for-data-centers_dsn14.pdf|Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory}}, DSN 2014.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​heterogeneous-reliability-memory-for-data-centers_dsn14.pdf|Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory}}, DSN 2014.
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​heterogeneous-reliability-memory-for-data-centers_dsn14.pdf|Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory}}, DSN 2014.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​heterogeneous-reliability-memory-for-data-centers_dsn14.pdf|Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory}}, DSN 2014.
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​chipper_hpca11.pdf|CHIPPER:​ A Low-Complexity Bufferless Deflection Router}}, HPCA 2011.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​chipper_hpca11.pdf|CHIPPER:​ A Low-Complexity Bufferless Deflection Router}}, HPCA 2011.
-  * {{https://​arxiv.org/​abs/​1510.00149|Deep Compression:​ Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding}}, ArXiv 2016.+  ​* {{ https://​web.stanford.edu/​~yatisht/​pubs/​darwin.pdf | Darwin: A genomics co-processor provides up to 15,000 x acceleration on long read assembly}}, ASPLOS 2018. 
 +  ​* {{https://​arxiv.org/​pdf/1510.00149.pdf|Deep Compression:​ Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding}}, ArXiv 2016.
   * {{diva99.pdf|DIVA:​ A Reliable Substrate for Deep Submicron Microarchitecture Design}}, MICRO 1999.   * {{diva99.pdf|DIVA:​ A Reliable Substrate for Deep Submicron Microarchitecture Design}}, MICRO 1999.
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​drange-dram-latency-based-true-random-number-generator_hpca19.pdf | D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput"​}},​ HPCA 2019.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​drange-dram-latency-based-true-random-number-generator_hpca19.pdf | D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput"​}},​ HPCA 2019.
   * {{perceptron_branch_predictor.pdf|Dynamic branch prediction with perceptrons}},​ HPCA 2001.   * {{perceptron_branch_predictor.pdf|Dynamic branch prediction with perceptrons}},​ HPCA 2001.
 +  * {{ http://​www.cs.princeton.edu/​courses/​archive/​spring16/​cos598F/​p229-smith.pdf | Efficient digital neurons for large scale cortical architectures}},​ ISCA 2014.
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​fst_asplos10.pdf|Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems}}, ASPLOS 2010.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​fst_asplos10.pdf|Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems}}, ASPLOS 2010.
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​dram-row-hammer_isca14.pdf|Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors}}, ISCA 2014.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​dram-row-hammer_isca14.pdf|Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors}}, ISCA 2014.
 +  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​Focus-low-latency-low-cost-video-analytics_osdi18.pdf | Focus: Querying Large Video Datasets with Low Latency and Low Cost}}, USENIX OSDI, 2018.
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​gatekeeper_FPGA-genome-prealignment-accelerator_bionformatics17.pdf|GateKeeper:​ A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping}}, Bioinformatics 2017.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​gatekeeper_FPGA-genome-prealignment-accelerator_bionformatics17.pdf|GateKeeper:​ A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping}}, Bioinformatics 2017.
-  ​* {{https://​arxiv.org/​pdf/​1711.01177.pdf| GRIM-Filter:​ Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies, ​ BMC Genomics, 2018}} +  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​GSDRAM-gather-scatter-dram_micro15.pdf | Gather-scatter DRAMin-DRAM address translation to improve the spatial locality of non-unit strided accesses}}, MICRO 2015.
-  ​* {{https://​people.inf.ethz.ch/​omutlu/​pub/​Focus-low-latency-low-cost-video-analytics_osdi18.pdf | FocusQuerying Large Video Datasets with Low Latency and Low Cost}}, Proceedings of the 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI), 2018.+
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​Google-consumer-workloads-data-movement-and-PIM_asplos18.pdf|Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks}},​ ASPLOS 2018.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​Google-consumer-workloads-data-movement-and-PIM_asplos18.pdf|Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks}},​ ASPLOS 2018.
 +  * {{https://​arxiv.org/​pdf/​1711.01177.pdf| GRIM-Filter:​ Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies}}, ​ BMC Genomics, 2018
 +  * {{ https://​arxiv.org/​pdf/​1807.05140.pdf | Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation}},​ SIGMETRICS 2018.
   * {{08192463.pdf|In-Datacenter Performance Analysis of a Tensor Processing Unit}}, ISCA 2017.   * {{08192463.pdf|In-Datacenter Performance Analysis of a Tensor Processing Unit}}, ISCA 2017.
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems}}, ISCA 2008. +  ​* {{http://​www.cs.utah.edu/​~rajeev/​pubs/​isca16-old.pdf | ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars}},​ ISCA 2016. 
-  * {{profiling_a_warehouse-scale_computer.pdf| "Profiling a Warehouse-scale Computer," ​ISCA, 2015.}}+  * {{https://​www.usenix.org/​event/​sec08/​tech/​full_papers/​halderman/​halderman.pdf | Lest we remember: cold-boot attacks on encryption keys}}, Communications of the ACM, 2009. 
 +  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​mph_usenix_security07.pdf|Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems}}, USENIX SECURITY 2007. 
 +  * {{http://​users.ece.cmu.edu/​~rausavar/​pubs/​mosaic-osr18.pdf | Mosaic: Enabling Application-Transparent Support for Multiple Page Sizes in Throughput Processors}},​ ACM SIGOPS Operating Systems Review 2018. 
 +  * {{ https://​arxiv.org/​pdf/​1805.03718.pdf | Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks}}, ISCA 2018. 
 +  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​page-overlays-for-fine-grained-memory-management_isca15.pdf | Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management}},​ ISCA 2015. 
 +<​del>  ​* {{https://​people.inf.ethz.ch/​omutlu/​pub/​parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems}}, ISCA 2008 (already presented in class).</​del>​ 
 +  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​pim-enabled-instructons-for-low-overhead-pim_isca15.pdf|PIM-Enabled Instructions:​ A Low-Overhead,​ Locality-Aware Processing-in-Memory Architecture}},​ ISCA, 2015. 
 +  * {{ http://​cccp.eecs.umich.edu/​papers/​ntclark-micro03.pdf | Processor acceleration through automated instruction set customization}},​ MICRO 2003. 
 +  * {{https://​static.googleusercontent.com/​media/​research.google.com/​en//​pubs/​archive/​44271.pdf| Profiling a Warehouse-scale Computer}}, ISCA, 2015.
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​raidr-dram-refresh_isca12.pdf|RAIDR:​ Retention-Aware Intelligent DRAM Refresh}}, ISCA 2012.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​raidr-dram-refresh_isca12.pdf|RAIDR:​ Retention-Aware Intelligent DRAM Refresh}}, ISCA 2012.
 +  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​flash-read-disturb-errors_dsn15.pdf| Read Disturb Errors in MLC NAND Flash Memory: Characterization,​ Mitigation, and Recovery}}, DSN, 2015.
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​rlmc_isca08.pdf|Self Optimizing Memory Controllers:​ A Reinforcement Learning Approach}}, ISCA 2008.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​rlmc_isca08.pdf|Self Optimizing Memory Controllers:​ A Reinforcement Learning Approach}}, ISCA 2008.
-  * {{spectre_attacks.pdf|Spectre Attacks: Exploiting Speculative Execution}}, ​arxiv.org 2017.+  * {{ https://​ieeexplore.ieee.org/​iel5/​6210/​16584/​00765950.pdf | Simultaneous Subordinate Microthreading (SSMT)}}, ISCA 1999. 
 +  * {{https://​spectreattack.com/​spectre.pdf|Spectre Attacks: Exploiting Speculative Execution}}, ​SP 2019.
   * {{p294-rajwar.pdf|Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution}},​ MICRO 2001.   * {{p294-rajwar.pdf|Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution}},​ MICRO 2001.
   * {{single_chip_multiprocessor.pdf|The Case for a Single-Chip Multiprocessor}},​ ASPLOS 1996.   * {{single_chip_multiprocessor.pdf|The Case for a Single-Chip Multiprocessor}},​ ASPLOS 1996.
 +  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​tcm_micro10.pdf| Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior}}, MICRO 2010.
 +  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​tldram_hpca13.pdf| Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture}},​ HPCA 2013.
   * {{10.1.1.708.3891.pdf|Understanding sources of inefficiency in general-purpose chips}}, ISCA 2010.   * {{10.1.1.708.3891.pdf|Understanding sources of inefficiency in general-purpose chips}}, ISCA 2010.
-  * {{https://people.inf.ethz.ch/omutlu/pub/qureshi_isca06.pdf|A Case for MLP-Aware Cache Replacement}},​ ISCA 2006. +  * {{https://www.cs.princeton.edu/~appel/papers/memerr.pdf | Using Memory Errors to Attack a Virtual Machine}}, IEEE Symposium on Security and Privacy 2003
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​pcm_isca09.pdf|Architecting Phase Change Memory as a Scalable DRAM Alternative}},​ ISCA 2009. +
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​mph_usenix_security07.pdf|Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems}}, USENIX SECURITY 2007. +
-  * {{https://​dl.acm.org/​citation.cfm?​id=3273986 | Mosaic: Enabling Application-Transparent Support for Multiple Page Sizes in Throughput Processors}},​ ACM SIGOPS Operating Systems Review 2018. +
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​tldram_hpca13.pdf| "​Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,"​ HPCA 2013}} +
-  * {{ https://​people.inf.ethz.ch/​omutlu/​pub/​data-center-network-errors-at-facebook_imc18.pdf | A Large Scale Study of Data Center Network Reliability}},​ Proceedings of the 18th ACM Internet Measurement Conference (IMC) 2018. +
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​page-overlays-for-fine-grained-memory-management_isca15.pdf | Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management}},​ ISCA 2015. +
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​pim-enabled-instructons-for-low-overhead-pim_isca15.pdf|"​PIM-Enabled Instructions:​ A Low-Overhead,​ Locality-Aware Processing-in-Memory Architecture,"​ ISCA, 2015.}} +
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​flash-read-disturb-errors_dsn15.pdf| "Read Disturb Errors in MLC NAND Flash Memory: Characterization,​ Mitigation, and Recovery",​ DSN, 2015}} +
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​tcm_micro10.pdf| “Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior,​” MICRO 2010}} +
-  * {{http://​ieeexplore.ieee.org/​document/​1199334/ ​| Using Memory Errors to Attack a Virtual Machine}}, IEEE Symposium on Security and Privacy 2003+
papers.1550682387.txt.gz · Last modified: 2019/02/20 18:06 by alserm