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--- papers [2019/02/21 11:35]
alserm
+++ papers [2019/04/20 08:39] (current)
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 ~~NOCACHE~~
 ====== Papers ======
+===== Paper preferences (Due: 4 March 2019, 11:59 pm Zurich) =====
+Please check the list of papers below and then enter your preferences on the paper you would like to present during the seminar using the following link:
+  * [[https://moodle-app2.let.ethz.ch/mod/ratingallocate/view.php?id=340139 | Submit your preferences]]
+===== Paper list =====
   * {{https://people.inf.ethz.ch/omutlu/pub/bless_isca09.pdf|A Case for Bufferless Routing in On-Chip Networks}}, ISCA 2009.
   * {{https://people.inf.ethz.ch/omutlu/pub/qureshi_isca06.pdf|A Case for MLP-Aware Cache Replacement}}, ISCA 2006.
@@ Line 12: / Line 21: @@
   * {{https://people.inf.ethz.ch/omutlu/pub/heterogeneous-reliability-memory-for-data-centers_dsn14.pdf|Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory}}, DSN 2014.
   * {{https://people.inf.ethz.ch/omutlu/pub/chipper_hpca11.pdf|CHIPPER: A Low-Complexity Bufferless Deflection Router}}, HPCA 2011.
-  * {{ https://web.stanford.edu/~yatisht/pubs/darwin.pdf | Turakhia, Yatish, Gill Bejerano, and William J. Dally. "Darwin: A genomics co-processor provides up to 15,000 x acceleration on long read assembly}}, ASPLOS 2018.
+  * {{ https://web.stanford.edu/~yatisht/pubs/darwin.pdf | Darwin: A genomics co-processor provides up to 15,000 x acceleration on long read assembly}}, ASPLOS 2018.
   * {{https://arxiv.org/pdf/1510.00149.pdf|Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding}}, ArXiv 2016.
   * {{diva99.pdf|DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design}}, MICRO 1999.
@@ Line 22: / Line 31: @@
   * {{https://people.inf.ethz.ch/omutlu/pub/Focus-low-latency-low-cost-video-analytics_osdi18.pdf | Focus: Querying Large Video Datasets with Low Latency and Low Cost}}, USENIX OSDI, 2018.
   * {{https://people.inf.ethz.ch/omutlu/pub/gatekeeper_FPGA-genome-prealignment-accelerator_bionformatics17.pdf|GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping}}, Bioinformatics 2017.
+  * {{https://people.inf.ethz.ch/omutlu/pub/GSDRAM-gather-scatter-dram_micro15.pdf | Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses}}, MICRO 2015.
   * {{https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18.pdf|Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks}}, ASPLOS 2018.
   * {{https://arxiv.org/pdf/1711.01177.pdf| GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies}},  BMC Genomics, 2018
@@ Line 30: / Line 40: @@
   * {{https://people.inf.ethz.ch/omutlu/pub/mph_usenix_security07.pdf|Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems}}, USENIX SECURITY 2007.
   * {{http://users.ece.cmu.edu/~rausavar/pubs/mosaic-osr18.pdf | Mosaic: Enabling Application-Transparent Support for Multiple Page Sizes in Throughput Processors}}, ACM SIGOPS Operating Systems Review 2018.
+  * {{ https://arxiv.org/pdf/1805.03718.pdf | Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks}}, ISCA 2018.
   * {{https://people.inf.ethz.ch/omutlu/pub/page-overlays-for-fine-grained-memory-management_isca15.pdf | Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management}}, ISCA 2015.
-  * {{https://people.inf.ethz.ch/omutlu/pub/parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems}}, ISCA 2008.
+<del>  * {{https://people.inf.ethz.ch/omutlu/pub/parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems}}, ISCA 2008 (already presented in class).</del>
   * {{https://people.inf.ethz.ch/omutlu/pub/pim-enabled-instructons-for-low-overhead-pim_isca15.pdf|PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture}}, ISCA, 2015.
   * {{ http://cccp.eecs.umich.edu/papers/ntclark-micro03.pdf | Processor acceleration through automated instruction set customization}}, MICRO 2003.
-  * {{profiling_a_warehouse-scale_computer.pdf| Profiling a Warehouse-scale Computer}}, ISCA, 2015.
+  * {{https://static.googleusercontent.com/media/research.google.com/en//pubs/archive/44271.pdf| Profiling a Warehouse-scale Computer}}, ISCA, 2015.
   * {{https://people.inf.ethz.ch/omutlu/pub/raidr-dram-refresh_isca12.pdf|RAIDR: Retention-Aware Intelligent DRAM Refresh}}, ISCA 2012.
   * {{https://people.inf.ethz.ch/omutlu/pub/flash-read-disturb-errors_dsn15.pdf| Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery}}, DSN, 2015.
   * {{https://people.inf.ethz.ch/omutlu/pub/rlmc_isca08.pdf|Self Optimizing Memory Controllers: A Reinforcement Learning Approach}}, ISCA 2008.
   * {{ https://ieeexplore.ieee.org/iel5/6210/16584/00765950.pdf | Simultaneous Subordinate Microthreading (SSMT)}}, ISCA 1999.
-  * {{spectre_attacks.pdf|Spectre Attacks: Exploiting Speculative Execution}}, arxiv.org 2017.
+  * {{https://spectreattack.com/spectre.pdf|Spectre Attacks: Exploiting Speculative Execution}}, SP 2019.
   * {{p294-rajwar.pdf|Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution}}, MICRO 2001.
   * {{single_chip_multiprocessor.pdf|The Case for a Single-Chip Multiprocessor}}, ASPLOS 1996.

Seminar in Computer Architecture - Spring 2019

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