papers
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
|
papers [2019/02/21 12:06] alserm |
papers [2019/04/20 08:39] (current) |
||
|---|---|---|---|
| Line 3: | Line 3: | ||
| - | ===== Paper preferences (Due: 25 February 2019, 11:59 pm Zurich) ===== | + | ===== Paper preferences (Due: 4 March 2019, 11:59 pm Zurich) ===== |
| - | Please check the list of papers below. Please enter your preferences on the paper you would like to present during the seminar. | + | Please check the list of papers below and then enter your preferences on the paper you would like to present during the seminar using the following link: |
| * [[https://moodle-app2.let.ethz.ch/mod/ratingallocate/view.php?id=340139 | Submit your preferences]] | * [[https://moodle-app2.let.ethz.ch/mod/ratingallocate/view.php?id=340139 | Submit your preferences]] | ||
| - | ===== Papers list ===== | + | ===== Paper list ===== |
| * {{https://people.inf.ethz.ch/omutlu/pub/bless_isca09.pdf|A Case for Bufferless Routing in On-Chip Networks}}, ISCA 2009. | * {{https://people.inf.ethz.ch/omutlu/pub/bless_isca09.pdf|A Case for Bufferless Routing in On-Chip Networks}}, ISCA 2009. | ||
| * {{https://people.inf.ethz.ch/omutlu/pub/qureshi_isca06.pdf|A Case for MLP-Aware Cache Replacement}}, ISCA 2006. | * {{https://people.inf.ethz.ch/omutlu/pub/qureshi_isca06.pdf|A Case for MLP-Aware Cache Replacement}}, ISCA 2006. | ||
| Line 31: | Line 31: | ||
| * {{https://people.inf.ethz.ch/omutlu/pub/Focus-low-latency-low-cost-video-analytics_osdi18.pdf | Focus: Querying Large Video Datasets with Low Latency and Low Cost}}, USENIX OSDI, 2018. | * {{https://people.inf.ethz.ch/omutlu/pub/Focus-low-latency-low-cost-video-analytics_osdi18.pdf | Focus: Querying Large Video Datasets with Low Latency and Low Cost}}, USENIX OSDI, 2018. | ||
| * {{https://people.inf.ethz.ch/omutlu/pub/gatekeeper_FPGA-genome-prealignment-accelerator_bionformatics17.pdf|GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping}}, Bioinformatics 2017. | * {{https://people.inf.ethz.ch/omutlu/pub/gatekeeper_FPGA-genome-prealignment-accelerator_bionformatics17.pdf|GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping}}, Bioinformatics 2017. | ||
| + | * {{https://people.inf.ethz.ch/omutlu/pub/GSDRAM-gather-scatter-dram_micro15.pdf | Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses}}, MICRO 2015. | ||
| * {{https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18.pdf|Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks}}, ASPLOS 2018. | * {{https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18.pdf|Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks}}, ASPLOS 2018. | ||
| * {{https://arxiv.org/pdf/1711.01177.pdf| GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies}}, BMC Genomics, 2018 | * {{https://arxiv.org/pdf/1711.01177.pdf| GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies}}, BMC Genomics, 2018 | ||
| Line 39: | Line 40: | ||
| * {{https://people.inf.ethz.ch/omutlu/pub/mph_usenix_security07.pdf|Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems}}, USENIX SECURITY 2007. | * {{https://people.inf.ethz.ch/omutlu/pub/mph_usenix_security07.pdf|Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems}}, USENIX SECURITY 2007. | ||
| * {{http://users.ece.cmu.edu/~rausavar/pubs/mosaic-osr18.pdf | Mosaic: Enabling Application-Transparent Support for Multiple Page Sizes in Throughput Processors}}, ACM SIGOPS Operating Systems Review 2018. | * {{http://users.ece.cmu.edu/~rausavar/pubs/mosaic-osr18.pdf | Mosaic: Enabling Application-Transparent Support for Multiple Page Sizes in Throughput Processors}}, ACM SIGOPS Operating Systems Review 2018. | ||
| + | * {{ https://arxiv.org/pdf/1805.03718.pdf | Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks}}, ISCA 2018. | ||
| * {{https://people.inf.ethz.ch/omutlu/pub/page-overlays-for-fine-grained-memory-management_isca15.pdf | Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management}}, ISCA 2015. | * {{https://people.inf.ethz.ch/omutlu/pub/page-overlays-for-fine-grained-memory-management_isca15.pdf | Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management}}, ISCA 2015. | ||
| - | * {{https://people.inf.ethz.ch/omutlu/pub/parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems}}, ISCA 2008. | + | <del> * {{https://people.inf.ethz.ch/omutlu/pub/parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems}}, ISCA 2008 (already presented in class).</del> |
| * {{https://people.inf.ethz.ch/omutlu/pub/pim-enabled-instructons-for-low-overhead-pim_isca15.pdf|PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture}}, ISCA, 2015. | * {{https://people.inf.ethz.ch/omutlu/pub/pim-enabled-instructons-for-low-overhead-pim_isca15.pdf|PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture}}, ISCA, 2015. | ||
| * {{ http://cccp.eecs.umich.edu/papers/ntclark-micro03.pdf | Processor acceleration through automated instruction set customization}}, MICRO 2003. | * {{ http://cccp.eecs.umich.edu/papers/ntclark-micro03.pdf | Processor acceleration through automated instruction set customization}}, MICRO 2003. | ||
| Line 48: | Line 50: | ||
| * {{https://people.inf.ethz.ch/omutlu/pub/rlmc_isca08.pdf|Self Optimizing Memory Controllers: A Reinforcement Learning Approach}}, ISCA 2008. | * {{https://people.inf.ethz.ch/omutlu/pub/rlmc_isca08.pdf|Self Optimizing Memory Controllers: A Reinforcement Learning Approach}}, ISCA 2008. | ||
| * {{ https://ieeexplore.ieee.org/iel5/6210/16584/00765950.pdf | Simultaneous Subordinate Microthreading (SSMT)}}, ISCA 1999. | * {{ https://ieeexplore.ieee.org/iel5/6210/16584/00765950.pdf | Simultaneous Subordinate Microthreading (SSMT)}}, ISCA 1999. | ||
| - | * {{spectre_attacks.pdf|Spectre Attacks: Exploiting Speculative Execution}}, arxiv.org 2017. | + | * {{https://spectreattack.com/spectre.pdf|Spectre Attacks: Exploiting Speculative Execution}}, SP 2019. |
| * {{p294-rajwar.pdf|Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution}}, MICRO 2001. | * {{p294-rajwar.pdf|Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution}}, MICRO 2001. | ||
| * {{single_chip_multiprocessor.pdf|The Case for a Single-Chip Multiprocessor}}, ASPLOS 1996. | * {{single_chip_multiprocessor.pdf|The Case for a Single-Chip Multiprocessor}}, ASPLOS 1996. | ||
papers.1550747209.txt.gz · Last modified: 2019/02/21 12:06 by alserm
Page Tools
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Noncommercial-Share Alike 4.0 International
