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• A Case for Bufferless Routing in On-Chip Networks, ISCA 2009.
• A Case for MLP-Aware Cache Replacement, ISCA 2006.
• A Large Scale Study of Data Center Network Reliability, ACM IMC 2018.
• A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing, ISCA 2015.
• A2: Analog malicious hardware, IEEE Symposium on Security and Privacy 2016.
• Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology, MICRO 2017.
• Architecting Phase Change Memory as a Scalable DRAM Alternative, ISCA 2009.
• Bottleneck Identification and Scheduling in Multithreaded Applications, ASPLOS 2012.
• Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory, DSN 2014.
• Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory, DSN 2014.
• CHIPPER: A Low-Complexity Bufferless Deflection Router, HPCA 2011.
• Darwin: A genomics co-processor provides up to 15,000 x acceleration on long read assembly, ASPLOS 2018.
• Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding, ArXiv 2016.
• DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design, MICRO 1999.
• D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput", HPCA 2019.
• Dynamic branch prediction with perceptrons, HPCA 2001.
• Efficient digital neurons for large scale cortical architectures, ISCA 2014.
• Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems, ASPLOS 2010.
• Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, ISCA 2014.
• Focus: Querying Large Video Datasets with Low Latency and Low Cost, USENIX OSDI, 2018.
• GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping, Bioinformatics 2017.
• Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses, MICRO 2015.
• Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks, ASPLOS 2018.
• GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies, BMC Genomics, 2018
• Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation, SIGMETRICS 2018.
• In-Datacenter Performance Analysis of a Tensor Processing Unit, ISCA 2017.
• ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars, ISCA 2016.
• Lest we remember: cold-boot attacks on encryption keys, Communications of the ACM, 2009.
• Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems, USENIX SECURITY 2007.
• Mosaic: Enabling Application-Transparent Support for Multiple Page Sizes in Throughput Processors, ACM SIGOPS Operating Systems Review 2018.
• Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks, ISCA 2018.
• Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management, ISCA 2015.
• Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems, ISCA 2008.
• PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture, ISCA, 2015.
• Processor acceleration through automated instruction set customization, MICRO 2003.
• Profiling a Warehouse-scale Computer, ISCA, 2015.
• RAIDR: Retention-Aware Intelligent DRAM Refresh, ISCA 2012.
• Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery, DSN, 2015.
• Self Optimizing Memory Controllers: A Reinforcement Learning Approach, ISCA 2008.
• Simultaneous Subordinate Microthreading (SSMT), ISCA 1999.
• Spectre Attacks: Exploiting Speculative Execution, arxiv.org 2017.
• Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution, MICRO 2001.
• The Case for a Single-Chip Multiprocessor, ASPLOS 1996.
• Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior, MICRO 2010.
• Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture, HPCA 2013.
• Understanding sources of inefficiency in general-purpose chips, ISCA 2010.
• Using Memory Errors to Attack a Virtual Machine, IEEE Symposium on Security and Privacy 2003