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papers [2019/02/28 16:24]
alserm
papers [2019/04/20 08:39] (current)
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   * {{ https://​arxiv.org/​pdf/​1805.03718.pdf | Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks}}, ISCA 2018.   * {{ https://​arxiv.org/​pdf/​1805.03718.pdf | Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks}}, ISCA 2018.
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​page-overlays-for-fine-grained-memory-management_isca15.pdf | Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management}},​ ISCA 2015.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​page-overlays-for-fine-grained-memory-management_isca15.pdf | Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management}},​ ISCA 2015.
-  ​* {{https://​people.inf.ethz.ch/​omutlu/​pub/​parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems}}, ISCA 2008.+<​del>  ​* {{https://​people.inf.ethz.ch/​omutlu/​pub/​parbs_isca08.pdf|Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems}}, ISCA 2008 (already presented in class).</​del>​
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​pim-enabled-instructons-for-low-overhead-pim_isca15.pdf|PIM-Enabled Instructions:​ A Low-Overhead,​ Locality-Aware Processing-in-Memory Architecture}},​ ISCA, 2015.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​pim-enabled-instructons-for-low-overhead-pim_isca15.pdf|PIM-Enabled Instructions:​ A Low-Overhead,​ Locality-Aware Processing-in-Memory Architecture}},​ ISCA, 2015.
   * {{ http://​cccp.eecs.umich.edu/​papers/​ntclark-micro03.pdf | Processor acceleration through automated instruction set customization}},​ MICRO 2003.   * {{ http://​cccp.eecs.umich.edu/​papers/​ntclark-micro03.pdf | Processor acceleration through automated instruction set customization}},​ MICRO 2003.
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   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​rlmc_isca08.pdf|Self Optimizing Memory Controllers:​ A Reinforcement Learning Approach}}, ISCA 2008.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​rlmc_isca08.pdf|Self Optimizing Memory Controllers:​ A Reinforcement Learning Approach}}, ISCA 2008.
   * {{ https://​ieeexplore.ieee.org/​iel5/​6210/​16584/​00765950.pdf | Simultaneous Subordinate Microthreading (SSMT)}}, ISCA 1999.   * {{ https://​ieeexplore.ieee.org/​iel5/​6210/​16584/​00765950.pdf | Simultaneous Subordinate Microthreading (SSMT)}}, ISCA 1999.
-  * {{spectre_attacks.pdf|Spectre Attacks: Exploiting Speculative Execution}}, ​arxiv.org 2017.+  * {{https://​spectreattack.com/​spectre.pdf|Spectre Attacks: Exploiting Speculative Execution}}, ​SP 2019.
   * {{p294-rajwar.pdf|Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution}},​ MICRO 2001.   * {{p294-rajwar.pdf|Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution}},​ MICRO 2001.
   * {{single_chip_multiprocessor.pdf|The Case for a Single-Chip Multiprocessor}},​ ASPLOS 1996.   * {{single_chip_multiprocessor.pdf|The Case for a Single-Chip Multiprocessor}},​ ASPLOS 1996.
papers.1551367487.txt.gz ยท Last modified: 2019/02/28 16:24 by alserm