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• 3D-stacked memory architectures for multi-core processors, International Symposium on Computer Architecture 2008.
• A Case for Bufferless Routing in On-Chip Networks , ISCA 2009.
• A case for exploiting subarray-level parallelism (SALP) in DRAM, ISCA 2012.
• A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap with Expressive Memory , ISCA 2018.
• A Logic-in-Memory Computer, IEEE Transactions on Computers 1970.
• A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing , ISCA 2015.
• A2: Analog malicious hardware , IEEE Symposium on Security and Privacy 2016.
• Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case , HPCA 2015.
• Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology , MICRO 2017.
• An Analysis of Persistent Memory Use with WHISPER , ASPLOS 2017.
• Architecting Phase Change Memory as a Scalable DRAM Alternative , ISCA 2009.
• Architecting Waferscale Processors - A GPU Case Study, HPCA 2019.
• Bottleneck Identification and Scheduling in Multithreaded Applications , ASPLOS 2012.
• Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory , DSN 2014.
• CHIPPER: A Low-Complexity Bufferless Deflection Router , HPCA 2011.
• CLKSCREW: Exposing the Perils of Security-Oblivious Energy Management , USENIX SECURITY 2017.
• ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs, MICRO 2019.
• CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators , ISCA 2019.
• CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability , ISCA 2019.
• Darwin-WGA: A Co-processor Provides Increased Sensitivity in Whole Genome Alignments with High Speedup , HPCA 2019.
• Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding , ArXiv 2016.
• DeepStore: In-Storage Acceleration for Intelligent Queries, MICRO 2019.
• Demystifying Workload–DRAM Interactions: An Experimental Study  , ACM SIGMETRICS 2019.
• Designing Vertical Processors in Monolithic 3D, ISCA 2019.
• DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design , MICRO 1999.
• Drammer: Deterministic Rowhammer Attacks on Mobile Platforms , CCS 2016.
• EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM, MICRO 2019.
• ELP2IM: Efficient and Low Power Bitwise Operation Processing in DRAM, HPCA 2020.
• Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors , ISCA 2014.
• High-Density Image Storage Using Approximate Memory Cells, ASPLOS 2016.
• In-Datacenter Performance Analysis of a Tensor Processing Unit , ISCA 2017.
• ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars , ISCA 2016.
• Lest we remember: cold-boot attacks on encryption keys , 17th USENIX Security Symposium 2008.
• Memory Hierarchy for Web Search , HPCA 2018.
• Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems , USENIX SECURITY 2007.
• Memristive Boltzmann machine: A hardware accelerator for combinatorial optimization and deep learning, HPCA 2016.
• New Attacks and Defense for Encrypted-Address Cache , ISCA 2019.
• Plasticine: A Reconfigurable Architecture For Parallel Patterns, ISCA 2017.
• Processor acceleration through automated instruction set customization , MICRO 2003.
• Profiling a Warehouse-scale Computer , ISCA 2015.
• Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , MICRO 2003.
• Rethinking the Memory Hierarchy for Modern Languages, MICRO 2018.
• Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors , HPCA 2003.
• Self Optimizing Memory Controllers: A Reinforcement Learning Approach , ISCA 2008.
• Shouji: A Fast and Efficient Pre-Alignment Filter for Sequence Alignment, Bioinformatics 2019.
• SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations, MICRO 2019.
• SneakySnake: A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs, arXiv 2019.
• Spectre Attacks: Exploiting Speculative Execution , IEEE Symposium on Security and Privacy 2019.
• Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution , MICRO 2001.
• The Case for a Single-Chip Multiprocessor , ASPLOS 1996.
• The Dirty-Block Index, ISCA 2014.
• The Locality Descriptor: A Holistic Cross-Layer Abstraction to Express Data Locality in GPUs, ISCA 2018.
• Three-dimensional integration of nanotechnologies for computing and data storage on a single chip , Nature 2017.
• Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture, HPCA 2013.
• Transactional Memory: Architectural Support for Lock-Free Data Structures , ISCA 1993.
• Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems , ISCA 2016.
• Using Memory Errors to Attack a Virtual Machine , IEEE Symposium on Security and Privacy 2003.
• Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches, MICRO 2006.
• Zorua: A Holistic Approach to Resource Virtualization in GPUs , MICRO 2016