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Seminar in Computer Architecture FS19: Course Webpage
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Computer Architecture FS19: Course Webpage
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Design of Digital Circuits SS19: Lecture Videos
readings
Table of Contents
Readings
Lecture 1 (20.02 Thu.)
Lecture 2 (27.02 Thu.)
Lecture 3 (12.03 Thu.)
Lecture 4 (19.03 Thu.)
Lecture 5 (26.03 Thu.)
Lecture 6 (02.04 Thu.)
Lecture 7 (09.04 Thu.)
Lecture 8 (23.04 Thu.)
Lecture 9 (30.04 Thu.)
Lecture 10 (07.05 Thu.)
Lecture 11 (21.05 Thu.)
Lecture 12 (28.05 Thu.)
Readings
Lecture 1 (20.02 Thu.)
Suggested (lecture 1):
G.E. Moore. "Cramming more components onto integrated circuits," Electronics magazine, 1965
B.C. Lee, E. Ipek, O. Mutlu, D. Burger, "Architecting Phase Change Memory as a Scalable DRAM Alternative," ISCA 2009
B. C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. Burger "Phase-Change Technology and the Future of Main Memory" IEEE Micro Top Picks 2010
N.P. Jouppi, C. Young, N. Patil, D. Patterson, G. Agrawal, R. Bajwa, S. Bates, S. Bhatia, N. Boden, A. Borchers, R. Boyle, P.-L. Cantin, C. Chao, C. Clark, J. Coriell, M. Daley, M. Dau, J. Dean, B. Gelb, T.V. Ghaemmaghami, R. Gottipati, W. Gulland, R. Hagmann, C.R. Ho, D. Hogberg, J. Hu, R. Hundt, D. Hurt, J. Ibarz, A. Jaffey, A. Jaworski, A. Kaplan, H. Khaitan, D. Killebrew, A. Koch, N. Kumar, S. Lacy, J. Laudon, J. Law, D. Le, C. Leary, Z. Liu, K. Lucke, A. Lundin, G. MacKean, A. Maggiore, M. Mahony, K. Miller, R. Nagarajan, R. Narayanaswami, R. Ni, K. Nix, T. Norrie, M. Omernick, N. Penukonda, A. Phelps, J. Ross, M. Ross, A. Salek, E. Samadiani, C. Severn, G. Sizikov, M. Snelham, J. Souter, D. Steinberg, A. Swing, M. Tan, G. Thorson, B. Tian, H. Toma, E. Tuttle, V. Vasudevan, R. Walter, W. Wang, E. Wilcox, D.H. Yoon, "In-Datacenter Performance Analysis of a Tensor Processing Unit,” ISCA 2017.
Y. Kim, R. Daly, J. Kim, C. Fallin, J.H. Lee, D. Lee, C. Wilkerson, K. Lai, O. Mutlu, "Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors," ISCA 2014
O. Mutlu, J. S. Kim, RowHammer: A Retrospective," arXiv, 2019
D. Senol Cali, J.S. Kim, S. Ghose, C. Alkan, and O. Mutlu, “Nanopore Sequencing Technology and Tools for Genome Assembly: Computational Analysis of the Current State, Bottlenecks and Future Directions,” Briefings in Bioinformatics, 2018
A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan, and O. Mutlu, "Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,” ASPLOS, 2018.
T.S. Kuhn, "The Structure of Scientific Revolutions," 1962
R. Jain, "The Art of Computer Systems Performance Analysis," 1991
Lecture 2 (27.02 Thu.)
Suggested (lecture 2):
V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, M.A. Kozuch, P.B. Gibbons, T.C. Mowry, "RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization," MICRO, 2013.
K. K. Chang, P. J. Nair, S. Ghose, D. Lee, M. K. Qureshi, O. Mutlu, "Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM," HPCA 2016
V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M.A. Kozuch, O. Mutlu, P.B. Gibbons, T.C. Mowry, “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” MICRO, 2017.
V. Seshadri, K. Hsieh, A. Boroumand, D. Lee, M.A. Kozuch, O.Mutlu, P.B. Gibbons, T.C. Mowry, "Fast Bulk Bitwise AND and OR in DRAM," IEEE CAL, 2015.
S. Li, C. Xu, Q. Zou, J. Zhao, Y. Lu, and Y. Xie, "Pinatubo: A Processing-in-Memory Architecture for Bulk Bitwise Operations in Emerging Non-volatile Memories," DAC, 2016
Lecture 3 (12.03 Thu.)
Suggested (lecture 3.a):
S.P. Muralidhara, L. Subramanian, O. Mutlu, M. Kandemir, T. Moscibroda, “Reducing Memory Interference in Multicore Systems via Application-aware Memory Channel Partitioning,” MICRO 2011
Yoongu Kim, Dongsu Han, Onur Mutlu, and Mor Harchol-Balter, "ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers" HPCA 2010
Yoongu Kim, Michael Papamichael, Onur Mutlu, and Mor Harchol-Balter, "Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior" MICRO 2010
Suggested (lecture 3.b):
Onur Mutlu and Thomas Moscibroda, "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems", ISCA 2008
Onur Mutlu and Thomas Moscibroda, "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors" MICRO 2007
Suggested (lecture 3.c):
M. Patel, J.S. Kim, O. Mutlu, "The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions," ISCA 2017
M. Qureshi, D.H. Kim, S. Khan, P. Nair, O. Mutlu, "AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems," DSN 2015
J. Liu, B. Jaiyen, R. Veras, O. Mutlu, "RAIDR: Retention-Aware Intelligent DRAM Refresh," ISCA 2012
Lecture 4 (19.03 Thu.)
Suggested (lecture 4):
S1.1
Gaurav Dhiman, Raid Ayoub, Tajana Rosing, "PDRAM: A Hybrid PRAM and DRAM Main Memory System", DAC 2009
S1.2
Gaurav Dhiman, Raid Ayoub, Tajana Rosing, "PDRAM: A Hybrid PRAM and DRAM Main Memory System", DAC 2009
Arvind Kumar, Zhe Wan Zhe Wan, Winfried W Wilcke, Winfried W. Wilcke, Subramanian S Iyer, Subramanian S. Iyer, "Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration", ACM Journal on Emerging Technologies in Computing Systems 2017
Saptadeep Pal, Daniel Petrisko, Adeel A. Bajwa, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar, "A Case for Packageless Processors", 2018 IEEE International Symposium on High Performance Computer Architecture
Lecture 5 (26.03 Thu.)
Suggested (lecture 5):
S2.1
Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie Kim, Michael A Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry, "Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology", MICRO 2017
Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Michael A. Kozuch, Phillip B. Gibbons, and Todd C. Mowry "RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization", MICRO 2013
Shuangchen Li, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie "DRISA: A DRAM-based Reconfigurable In-Situ Accelerator", MICRO 2017
Quan Deng, Lei Jiang, Youtao Zhang, Minxuan Zhang ,Jun Yang "DrAcc: a DRAM based Accelerator for Accurate CNN Inference", DAC 2018
Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Ravi Iyer, Dennis M. Sylvester, David Theodore Blaauw, "Neural cache: bit-serial in-cache acceleration of deep neural networks" ISCA 2018
S2.2
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy "Simultaneous multithreading: maximizing on-chip parallelism", ISCA 1995
Dean M. Tullsen, S. Eggers ,Joel S. Emer, Henry M Levy, Jack Lee Jay Lo, Rebecca L Stamm "Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor", ISCA 1996
Hiroaki Hirata, Kozo Kimura, Satoshi Nagamine, Yoshiyuki Mochizuki, Akio Nishimura, Yoshimori Nakase, Teiji Nishizawa "An elementary processor architecture with simultaneous instruction issuing from multiple threads", ISCA 1992
Wayne Yamamoto, Mario Nemirovsky "Increasing superscalar performance through multistreaming", PACT 1995
Multi-core processors
Multi-core processors II
Multi-core: Why?
Multi-core: Evolution
Lecture 6 (02.04 Thu.)
Suggested (lecture 6):
S3.1
Tilo Müller, Michael Spreitzenbarth, “FROST: Forensic Recovery of Scrambled Telephones”, ACNS 2013
Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Reetuparna Das, Todd Austin, “Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors”, HPCA 2017
Tilo Müller, Felix C. Freiling, Andreas Dewald, “TRESOR Runs Encryption Securely Outside RAM”, USENIX Security 2011
Lois Orosa, Yaohua Wang, Ivan Puddu, Mohammad Sadrosadati, Kaveh Razavi, Juan Gómez-Luna, Hasan Hassan, Nika Mansouri-Ghiasi, Arash Tavakkol, Minesh Patel, Jeremie Kim, Vivek Seshadri, Uksong Kang, Saugata Ghose, Rodolfo Azevedo, Onur Mutlu, “Dataplant: Enhancing System Security with Low-Cost In-DRAM Value Generation Primitives”, arXiv 2019
Muhammad Naveed , Erman Ayday, Ellen W Clayton, Jacques Fellay, Carl A. Gunter ,Jean-Pierre Hubaux, Bradley A. Malin, Xiaofeng Wang, “Privacy in the Genomic Era”, ACSUR 2015
Oded Regev, “On Lattices, Learning with Errors, Random Linear Codes, and Cryptography”, JACM 2009
Moni Naor, Gil Segev, “Public-Key Cryptosystems Resilient to Key Leakage”, CRYPTO 2009
Lecture 7 (09.04 Thu.)
Suggested (lecture 7):
S4.1
Luiz Andre Barroso, Kourosh Gharachorloo, and Edouard Bugnion, "Memory System Characterization of Commercial Workloads", ISCA 1998
Amirali Boroumand, Saugata Ghose, Youngsok Kim, Rachata Ausavarungnirun, Eric Shiu, Rahul Thakur, Daehyun Kim, Aki Kuusela, Allan Knies, Parthasarathy Ranganathan, Onur Mutlu, "Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks", ASPLOS 2018
Vijay Janapa Reddi, Benjamin C Lee, Trishul Madhukar Chilimbi, Kushagra Vaid, "Web Search Using Mobile Cores: Quantifying and Mitigating the Price of Efficiency", ISCA 2010
J. Adam Butts and Gurindar S. Sohi, "Use-Based Register Caching with Decoupled Indexing", ISCA 2004
Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, Onur Mutlu, Srinivas Devadas, "Banshee: Bandwidth-Efficient DRAM Caching via Software/Hardware Cooperation", MICRO 2017
S4.2
José A. Joao, Onur Mutlu, and Yale N. Patt, "Flexible Reference Counting-Based Hardware Acceleration for Garbage Collection", ISCA 2009
Nandita Vijaykumar, Abhilasha Jain, Diptesh Majumdar, Kevin Hsieh, Gennady Pekhimenko, Eiman Ebrahimi, Nastaran Hajinazar, Phillip B. Gibbons and Onur Mutlu, "A Case for Richer Cross-layer Abstractions: Bridging the Semantic Gap with Expressive Memory", ISCA 2018
Bob Colwell, Edward F. Gehringer, and E. Douglas Jensen, "Performance Effects of Architectural Complexity in the Intel 432", ACM TOCS 1988
William J. Dally and James T. Kajiya, "An Object Oriented Architecture", ISCA 1985
Erik G. Hallnor and Steven K. Reinhardt, "A Fully Associative Software-Managed Cache Design", ISCA 2000
Lecture 8 (23.04 Thu.)
Suggested (lecture 8):
S5.1
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt, "Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures", ASPLOS 2009
Jose A. Joao,, M. Aater Suleman, Onur Mutlu, Yale N. Patt, "Bottleneck Identification and Scheduling in Multithreaded Applications", ASPLOS 2012
Christian Jacobi, Timothy Slegel, Dan Greiner, "Transactional Memory Architecture and Implementation for IBM System z", MICRO 2012
Dave Christie, Jae-Woong Chung, Stephan Diestelhorst, Michael Hohmuth, Martin Pohlack, Christof Fetzer, Martin Nowack, Torvald Riegel, Pascal Felber, Patrick Marlier, Etienne Rivière, "Evaluation of AMD’s Advanced Synchronization Facility Within a Complete Transactional Memory Stack", EuroSys 2010
Dave Dice, Yossi Lev, Mark Moir, Dan Nussbaum, "Early Experience with a Commercial Hardware Transactional Memory Implementation", ASPLOS 2009
S5.2
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt, "Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures", ASPLOS 2009
Jose A. Joao,, M. Aater Suleman, Onur Mutlu, Yale N. Patt, "Bottleneck Identification and Scheduling in Multithreaded Applications", ASPLOS 2012
Christian Jacobi, Timothy Slegel, Dan Greiner, "Transactional Memory Architecture and Implementation for IBM System z", MICRO 2012
Dave Christie, Jae-Woong Chung, Stephan Diestelhorst, Michael Hohmuth, Martin Pohlack, Christof Fetzer, Martin Nowack, Torvald Riegel, Pascal Felber, Patrick Marlier, Etienne Rivière, "Evaluation of AMD’s Advanced Synchronization Facility Within a Complete Transactional Memory Stack", EuroSys 2010
Dave Dice, Yossi Lev, Mark Moir, Dan Nussbaum, "Early Experience with a Commercial Hardware Transactional Memory Implementation", ASPLOS 2009
Lecture 9 (30.04 Thu.)
Suggested (lecture 9):
S6.1
K. Hegde, H. Asghari-Moghaddam, M. Pellauer, N. Crago, A. Jaleel, E. Solomonik, Joel S. Emer, Christopher W Fletcher,"ExTensor: An Accelerator for Sparse Tensor Algebra", MICRO 2019
Ashish Gondimalla,Noah Chesnut,Mithuna Shamabhat Thottethodii, T N Vijaykumar, "SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks", MICRO 2019
Vivek Seshadri, Gennady Pekhimenko, Olatunji Ruwase, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry, Trishul M. Chilimbi, "Page overlays: an enhanced virtual memory framework to enable fine-grained memory management", ISCA 2015
Eric Qin, Ananda Samajdar, Hyoukjun Kwon, Vineet Nadella, Sudarshan Srinivasan, Dipankar Das, Bharat Kaul, Tushar Krishna, "SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training", HPCA 2020
S6.2
Arvind K. Sujeeth, HyoukJoong Lee, Kevin J. Brown, Tiark Rompf, Hassan Chafi, Michael Wu, Anand R. Atreya, Martin Odersky, Kunle Olukotun, "OptiML: An Implicitly Parallel Domain-Specific Language for Machine Learning", ICML 2011
Koeplinger D, Feldman M, Prabhakar R, Zhang Y, Hadjis S, Fiszel R, Zhao T, Nardi L, Pedram A, Kozyrakis C, Olukotun K. "Spatial: a language and compiler for application accelerators", PLDI 2018
Raghu Prabhakar, David Koeplinger, Kevin J. Brown, HyoukJoong Lee, Christopher De Sa, Christos Kozyrakis, Kunle Olukotun, "Generating Configurable Hardware from Parallel Patterns", ASPLOS 2016
David Koeplinger, Raghu Prabhakar, Yaqi Zhang, Christina Delimitrou, Christos Kozyrakis, Kunle Olukotun, "Automatic Generation of Efficient Accelerators for Reconfigurable Hardware", ISCA 2016
Lecture 10 (07.05 Thu.)
Suggested (lecture 10):
S7.1
Discussed Papers
S. Koppula, L. Orosa, A. G. Yaglikci, R. Azizi, T. Shahroodi, K. Kanellopoulos, and O. Mutlu, "EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM," MICRO, 2019
K. Chang, A. Kashyap, H. Hassan, S. Khan, K. Hsieh, D. Lee, S. Ghose, G. Pekhimenko, T. Li, O. Mutlu, "Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization," SIGMETRICS 2016
K. Chang, A.G. Yaglikci, S. Ghose, A. Agrawal, N. Chatterjee, A. Kashyap, D. Lee, M. O'Connor, H. Hassan, O. Mutlu, "Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms," SIGMETRICS, 2017.
Jiajun Li, Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong, Jingya Wu, Xiaowei Li, "SmartShuttle: Optimizing Off-Chip Memory Accesses for Deep Learning Accelerators," DATE, Dresden, 2018.
M. Gao, J. Pu, X. Yang, M. Horowitz, and C. Kozyrakis, “TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory,” ASPLOS, 2017.
Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Reetuparna Das, Todd Austin, “Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors”, HPCA 2017
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Khan, Vivek Seshadri, Kevin Chang, and Onur Mutlu, "Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case" HPCA 2015
Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, and Onur Mutlu, "Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture", HPCA 2013
Related Papers
D. Lee, S. Khan, L. Subramanian, S. Ghose, R. Ausavarungnirun, G. Pekhimenko, V. Seshadri, O. Mutlu, "Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms,” SIGMETRICS 2017
K. Kanellopoulos, N. Vijaykumar, C. Giannoula, R. Azizi, S. Koppula, N. M. Ghiasi, T. Shahroodi, J. Gomez-Luna, and O. Mutlu, "SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations", MICRO, 2019
Yixin Luo, Sriram Govindan, Bikash Sharma, Mark Santaniello, Justin Meza, Aman Kansal, Jie Liu, Badriddine Khessib, Kushagra Vaid, and Onur Mutlu, "Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory" DSN 2014
Lecture 11 (21.05 Thu.)
Suggested (lecture 11):
S8.1
Discussed Papers
Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, Mike Hamburg, "Meltdown: Reading Kernel Memory from User Space", USENIX Security 2018
Jo Van Bulck, Marina Minkin, Ofir Weisse, Daniel Genkin, Baris Kasikci, Frank Piessens, Mark Silberstein, Thomas F. Wenisch, Yuval Yarom, Raoul Strackx, " Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution", USENIX Security 2018
Tyler Hunt, Zhiting Zhu, Yuanzhong Xu, Simon Peter, and Emmett Witchel ,"Ryoan: A Distributed Sandbox for Untrusted Computation on Secret Data", OSDI 2016
Guoxing Chen, Sanchuan Chen, Yuan Xiao, Yinqian Zhang, Zhiqiang Lin, Ten H. Lai, "SGXPECTREAttacks: Leaking Enclave Secrets via Speculative Execution", arXiv 2018
S8.2
Discussed Papers
Georg T. Becker, Francesco Regazzoni, Christof Paar,and Wayne P. Burleson,"Stealthy Dopant-Level Hardware Trojans", CHES 2013
Lang Lin, Markus Kasper, Tim G ̈uneysu,Christof Paar†, and Wayne Burleson, "Trojan Side-Channels: Lightweight HardwareTrojans through Side-Channel Engineering", CHES 2009
Lecture 12 (28.05 Thu.)
Suggested (lecture 12):
S9.1
Discussed Papers
Vivek Seshadri, Abhishek Bhowmick, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, and Todd C. Mowry, "The Dirty-Block Index", ISCA 2014.
Chang Joo Lee, Veynu Narasiman, Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt, "DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems", HPS Technical Report, TR-HPS-2010-002, April 2010.
Gokhan Memik, Glenn Reinman, and William H. Mangione-Smith. "Just say no: Benefits of early cache miss determination." HPCA 2003.
Guanghui Liu, "ECC-cache: A novel low power scheme to protect large-capacity L2 caches from transiant faults", In 2009 Fifth International Conference on Information Assurance and Security, 2009.
Johnathan Alsop, Matthew D. Sinclair, Srikant Bharadwaj, Alexandru Dutu, Anthony Gutierrez, Onur Kayiran, Michael LeBeane, Sooraj Puthoor, Xianwei Zhang, Tsung Tai Yeh, Bradford M. Beckmann, "Optimizing GPU cache policies for MI workloads", In 2019 IEEE International Symposium on Workload Characterization (IISWC) 2019.
Zhe Wang, Samira M. Khan, and Daniel A. Jiménez. "Improving writeback efficiency with decoupled last-write prediction", ISCA 2012.
Related Papers
V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, M.A. Kozuch, P.B. Gibbons, T.C. Mowry, "RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization," MICRO, 2013.
V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M.A. Kozuch, O. Mutlu, P.B. Gibbons, T.C. Mowry, “Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology,” MICRO, 2017.
Gabriel H. Loh and Mark D. Hill, "Efficiently enabling conventional block sizes for very large die-stacked DRAM caches", MICRO 2011
Samira M. Khan, Alaa R. Alameldeen, Chris Wilkerson, Jaydeep Kulkarni, and Daniel A. Jimenez., "Improving multi-core performance using mixed-cell cache architecture", HPCA 2013
Mainak Chaudhuri, Jayesh Gaur, Sreenivas Subramoney, "Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth", ICCD 2019.
S9.2
Discussed Papers
Van Der Veen, Victor, Yanick Fratantonio, Martina Lindorfer, Daniel Gruss, Clémentine Maurice, Giovanni Vigna, Herbert Bos, Kaveh Razavi, and Cristiano Giuffrida, "Drammer: Deterministic Rowhammer Attacks on Mobile Platforms", CCS 2016.
Y. Kim, R. Daly, J. Kim, C. Fallin, J.H. Lee, D. Lee, C. Wilkerson, K. Lai, O. Mutlu, "Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors," ISCA 2014
O. Mutlu, J. S. Kim, RowHammer: A Retrospective," arXiv, 2019
Related Papers
Jeremie S. Kim, Minesh Patel, A. Giray Yağlıkçı, Hasan Hassan, Roknoddin Azizi, Lois Orosa, Onur Mutlu, "Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques", ISCA 2020
Lucian Cojocar, Jeremie Kim, Minesh Patel, Lillian Tsai, Stefan Saroiu, Alec Wolman, and Onur Mutlu, "Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers", Proceedings of the 41st IEEE Symposium on Security and Privacy (S&P), San Francisco, CA, USA, May 2020.
Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi, "TRRespass: Exploiting the Many Sides of Target Row Refresh", Proceedings of the 41st IEEE Symposium on Security and Privacy (S&P), San Francisco, CA, USA, May 2020.
Ristenpart, Thomas, Eran Tromer, Hovav Shacham, and Stefan Savage. "Hey, you, get off of my cloud: exploring information leakage in third-party compute clouds." In Proceedings of the 16th ACM conference on Computer and communications security, pp. 199-212. 2009.
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