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readings [2020/05/28 17:30] – [Lecture 11 (21.05 Thu.)] kanellokreadings [2020/05/29 10:26] (current) – external edit 127.0.0.1
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 === S1.2 === === S1.2 ===
-  * {{http://seelab.ucsd.edu/papers/gdhiman_dac09.pdf| Gaurav Dhiman, Raid Ayoub, Tajana Rosing, "PDRAM: A Hybrid PRAM and DRAM Main Memory System", DAC 2009}}+  * [[http://seelab.ucsd.edu/papers/gdhiman_dac09.pdf| Gaurav Dhiman, Raid Ayoub, Tajana Rosing, "PDRAM: A Hybrid PRAM and DRAM Main Memory System", DAC 2009]] 
 +  * {{2976742.pdf| Arvind Kumar, Zhe  Wan Zhe Wan, Winfried W Wilcke, Winfried W. Wilcke, Subramanian S Iyer, Subramanian S. Iyer, "Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration", ACM Journal on Emerging Technologies in Computing Systems 2017}} 
 +  * {{08327030.pdf | Saptadeep Pal, Daniel Petrisko, Adeel A. Bajwa, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar, "A Case for Packageless Processors", 2018 IEEE International Symposium on High Performance Computer Architecture}}
  
  
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    === S2.2  ===    === S2.2  ===
-   * {{ https://dl.acm.org/doi/10.1145/223982.224449 +   * {{ smt.pdf 
 Dean M. Tullsen, Susan J. Eggers, Henry M. Levy "Simultaneous multithreading: maximizing on-chip parallelism", ISCA 1995 }} Dean M. Tullsen, Susan J. Eggers, Henry M. Levy "Simultaneous multithreading: maximizing on-chip parallelism", ISCA 1995 }}
-   * {{ https://dl.acm.org/doi/10.1145/232974.232993 | Dean M. Tullsen, S. Eggers ,Joel S. Emer, Henry M Levy, Jack Lee Jay Lo, Rebecca L Stamm+   * {{ exp_choice.pdf | Dean M. Tullsen, S. Eggers ,Joel S. Emer, Henry M Levy, Jack Lee Jay Lo, Rebecca L Stamm
 "Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor", ISCA 1996}} "Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor", ISCA 1996}}
-   * {{ https://dl.acm.org/doi/10.1145/146628.1397103 +   * {{ elem.pdf 
 Hiroaki  Hirata, Kozo  Kimura, Satoshi  Nagamine, Yoshiyuki  Mochizuki, Akio  Nishimura, Yoshimori  Nakase, Teiji  Nishizawa  Hiroaki  Hirata, Kozo  Kimura, Satoshi  Nagamine, Yoshiyuki  Mochizuki, Akio  Nishimura, Yoshimori  Nakase, Teiji  Nishizawa 
 "An elementary processor architecture with simultaneous instruction issuing from multiple threads", ISCA 1992}}  "An elementary processor architecture with simultaneous instruction issuing from multiple threads", ISCA 1992}} 
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    *{{ https://courses.cs.ut.ee/MTAT.07.022/2013_fall/uploads/Main/tiit-report | Georg T. Becker, Francesco Regazzoni, Christof Paar,and Wayne P. Burleson,"Stealthy Dopant-Level Hardware Trojans", CHES 2013}}    *{{ https://courses.cs.ut.ee/MTAT.07.022/2013_fall/uploads/Main/tiit-report | Georg T. Becker, Francesco Regazzoni, Christof Paar,and Wayne P. Burleson,"Stealthy Dopant-Level Hardware Trojans", CHES 2013}}
 +   *{{ https://www.iacr.org/archive/ches2009/57470383/57470383.pdf | Lang Lin, Markus Kasper, Tim G ̈uneysu,Christof Paar†, and Wayne Burleson, "Trojan Side-Channels: Lightweight HardwareTrojans through Side-Channel Engineering", CHES 2009}}
  
 ===== Lecture 12 (28.05 Thu.) ===== ===== Lecture 12 (28.05 Thu.) =====
readings.1590687018.txt.gz · Last modified: 2020/05/28 17:30 by kanellok