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• A Case for Bufferless Routing in On-Chip Networks, ISCA 2009.
• A case for exploiting subarray-level parallelism (SALP) in DRAM, ISCA 2012.
• A Case for Intelligent RAM, MICRO 1997
• A Case for MLP-Aware Cache Replacement, ISCA 2006.
• A case for toggle-aware compression for GPU systems, HPCA 2016
• A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data Locality, MICRO 2000
• A Logic-in-Memory Computer, IEEE Trans. Comput., 1970
• Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies, MICRO 2018
• Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology, MICRO 2017.
• Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches, PACT 2012.
• Biscuit: A Framework for Near-Data Processing of Big Data Workloads, ISCA 2016
• Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics, MICRO 2020
• BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, HPCA 2021
• CAPE: A Content-Addressable Processing Engine, HPCA 2021
• CHIPPER: A Low-Complexity Bufferless Deflection Router, HPCA 2011.
• CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off, ISCA 2020.
• Classifying memory access patterns for prefetching, ASPLOS 2020
• Computer structures: What have we learned from the PDP-11?, ISCA 1976
• CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators
• ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs, MICRO 2019
• Custom-fit Processors: Letting Applications Define Architectures, MICRO 1996
• D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput, HPCA 2019.
• Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts via Data Duplication, MICRO 2018
• DRISA: A DRAM-based Reconfigurable In-Situ Accelerator, MICRO 2017
• Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding, ArXiv 2016.
• DeepStore: In-Storage Acceleration for Intelligent Queries, MICRO 2019
• DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design, MICRO 1999.
• Dynamic branch prediction with perceptrons, HPCA 2001.
• EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM, MICRO 2019
• Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems, ASPLOS 2010.
• FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching, MICRO 2020
• Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, ISCA 2014.
• GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis, MICRO 2020
• Improving DRAM Performance by Parallelizing Refreshes with Accesses, HPCA 2014
• ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars, ISCA 2016.
• Leveraging EM Side-Channel Information to Detect Rowhammer Attacks, IEEE Symposium on Security and Privacy, 2020
• Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM, HPCA 2016
• Mondrian Memory Protection, ASPLOS 2002
• Mirage cores: the illusion of many out-of-order cores using in-order hardware, MICRO 2017
• Multiscalar Processors, ISCA 1995.
• New Attacks and Defense for Encrypted-Address Cache, ISCA 2019
• Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management, ISCA 2015.
• Plundervolt: Software-based Fault Injection Attacks against Intel SGX, IEEE Symposium on Security and Privacy 2020.
• Parallel Automata Processor, ISCA 2007
• PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture, ISCA, 2015.
• Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design, HPCA 2021
• Profiling a Warehouse-scale Computer, ISCA, 2015.
• Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation, MICRO 2003.
• Reducing Solid-state Drive Read Latency by Optimizing Read-retry, ASPLOS 2021
• Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques, ISCA 2020.
• Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors, HPCA 2003.
• Self Optimizing Memory Controllers: A Reinforcement Learning Approach, ISCA 2008.
• SIMDRAM: A Framework for Bit-Serial SIMD Processing Using DRAM, ASPLOS 2021
• Simultaneous Subordinate Microthreading (SSMT), ISCA 1999.
• Single-chip microprocessor that communicates directly using light, Nature 2015
• Slipstream processors: Improving both performance and fault tolerance, ASPLOS 2000.
• SneakySnake: A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs, Bioinformatics 2020
• Spectre Attacks: Exploiting Speculative Execution, IEEE Symposium on Security and Privacy 2019
• Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution, MICRO 2001.
• Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data, MICRO 2019
• SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures, HPCA 2021
• The Alpha 21264 Microprocessor, IEEE Micro 1999
• The Dirty-Block Index, ISCA 2014
• The Locality Descriptor: A Holistic Cross-Layer Abstraction to Express Data Locality in GPUs, ISCA 2018
• The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework, ISCA, 2020
• The Warp Computer: Architecture, Implementation, and Performance, IEEE TC 1987
• Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture, HPCA 2013.
• TRRespass: Exploiting the Many Sides of Target Row Refresh, IEEE Symposium on Security and Privacy, 2020
• Very Long Instruction Word Architectures and the ELI-512, ISCA 1983
• Voltage Emergency Prediction: Using Signatures to Reduce Operating Margins, HPCA 2009