Seminar in Computer Architecture - Spring 2021

User Tools

Site Tools

Trace:
papers

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Last revisionBoth sides next revision
papers [2021/03/04 20:49] – alsermpapers [2021/03/04 21:01] – alserm
Line 13: Line 13:
   * [[ https://www.pdl.cmu.edu/PDL-FTP/NVM/toggle-aware-compression-for-GPUs_hpca16.pdf | A case for toggle-aware compression for GPU systems, HPCA 2016 ]]   * [[ https://www.pdl.cmu.edu/PDL-FTP/NVM/toggle-aware-compression-for-GPUs_hpca16.pdf | A case for toggle-aware compression for GPU systems, HPCA 2016 ]]
   * {{ 00898056.pdf | A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data Locality, MICRO 2000 }}   * {{ 00898056.pdf | A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data Locality, MICRO 2000 }}
 +  * [[ https://safari.ethz.ch/architecture_seminar/fall2020/lib/exe/fetch.php?media=05008902.pdf | A Logic-in-Memory Computer, IEEE Trans. Comput., 1970 ]]
   * [[ https://people.csail.mit.edu/sanchez/papers/2018.ams.micro.pdf | Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies, MICRO 2018 ]]   * [[ https://people.csail.mit.edu/sanchez/papers/2018.ams.micro.pdf | Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies, MICRO 2018 ]]
   * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/exe/fetch.php?tok=66e666&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fambit-bulk-bitwise-dram_micro17.pdf | Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology, MICRO 2017. ]]   * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/exe/fetch.php?tok=66e666&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fambit-bulk-bitwise-dram_micro17.pdf | Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology, MICRO 2017. ]]
Line 22: Line 23:
   * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/exe/fetch.php?tok=1f090d&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fchipper_hpca11.pdf | CHIPPER: A Low-Complexity Bufferless Deflection Router, HPCA 2011. ]]   * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/exe/fetch.php?tok=1f090d&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fchipper_hpca11.pdf | CHIPPER: A Low-Complexity Bufferless Deflection Router, HPCA 2011. ]]
   * [[ https://people.inf.ethz.ch/omutlu/pub/CLR-DRAM_capacity-latency-reconfigurable-DRAM_isca20.pdf | CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off, ISCA 2020. ]]   * [[ https://people.inf.ethz.ch/omutlu/pub/CLR-DRAM_capacity-latency-reconfigurable-DRAM_isca20.pdf | CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off, ISCA 2020. ]]
 +  * [[ https://people.ucsc.edu/~hlitz/papers/asplos2020.pdf | Classifying memory access patterns for prefetching, ASPLOS 2020 ]]
   * [[ https://dl.acm.org/doi/pdf/10.1145/285930.285974?casa_token=5EnBI-YqPtsAAAAA%3A3U5ZOafYDoMIILhGg8ykpIS4O-vx4dkrNGHP4UD4yCi8VH-nC3rgGEK5QNAg3-fVHmc452R809CNkg | Computer structures: What have we learned from the PDP-11?, ISCA 1976 ]]   * [[ https://dl.acm.org/doi/pdf/10.1145/285930.285974?casa_token=5EnBI-YqPtsAAAAA%3A3U5ZOafYDoMIILhGg8ykpIS4O-vx4dkrNGHP4UD4yCi8VH-nC3rgGEK5QNAg3-fVHmc452R809CNkg | Computer structures: What have we learned from the PDP-11?, ISCA 1976 ]]
   * [[ https://people.inf.ethz.ch/omutlu/pub/CONDA-coherence-for-near-data-accelerators_isca19.pdf | CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators ]]   * [[ https://people.inf.ethz.ch/omutlu/pub/CONDA-coherence-for-near-data-accelerators_isca19.pdf | CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators ]]
 +  * [[ https://parallel.princeton.edu/papers/micro19-gao.pdf | ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs, MICRO 2019 ]]
   * {{ 00566472.pdf | Custom-fit Processors: Letting Applications Define Architectures, MICRO 1996 }}   * {{ 00566472.pdf | Custom-fit Processors: Letting Applications Define Architectures, MICRO 1996 }}
 +  * [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?tok=388edc&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fdrange-dram-latency-based-true-random-number-generator_hpca19.pdf | D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput, HPCA 2019. ]]
 +  * [[ https://hps.ece.utexas.edu/pub/lin_micro18.pdf | Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts via Data Duplication, MICRO 2018 ]]
 +  * [[ https://safari.ethz.ch/architecture_seminar/fall2020/lib/exe/fetch.php?media=3123939.3123977.pdf | DRISA: A DRAM-based Reconfigurable In-Situ Accelerator, MICRO 2017 ]]
   * [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?tok=602468&media=https%3A%2F%2Farxiv.org%2Fpdf%2F1510.00149.pdf | Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding, ArXiv 2016. ]]   * [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?tok=602468&media=https%3A%2F%2Farxiv.org%2Fpdf%2F1510.00149.pdf | Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding, ArXiv 2016. ]]
   * [[ https://jianh.web.engr.illinois.edu/papers/deepstore.pdf | DeepStore: In-Storage Acceleration for Intelligent Queries, MICRO 2019 ]]   * [[ https://jianh.web.engr.illinois.edu/papers/deepstore.pdf | DeepStore: In-Storage Acceleration for Intelligent Queries, MICRO 2019 ]]
Line 39: Line 45:
   * [[ https://people.inf.ethz.ch/omutlu/pub/lisa-dram_hpca16.pdf | Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM, HPCA 2016 ]]   * [[ https://people.inf.ethz.ch/omutlu/pub/lisa-dram_hpca16.pdf | Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM, HPCA 2016 ]]
   * [[ https://www.cs.utexas.edu/users/witchel/pubs/mmp-asplos2002.pdf | Mondrian Memory Protection, ASPLOS 2002 ]]   * [[ https://www.cs.utexas.edu/users/witchel/pubs/mmp-asplos2002.pdf | Mondrian Memory Protection, ASPLOS 2002 ]]
 +  * [[ http://cccp.eecs.umich.edu/papers/shrupad-micro17.pdf | Mirage cores: the illusion of many out-of-order cores using in-order hardware, MICRO 2017 ]]
   * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/exe/fetch.php?media=10.1.1.20.8558.pdf | Multiscalar Processors, ISCA 1995. ]]   * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/exe/fetch.php?media=10.1.1.20.8558.pdf | Multiscalar Processors, ISCA 1995. ]]
 +  * [[ https://memlab.ece.gatech.edu/papers/ISCA_2019_1.pdf | New Attacks and Defense for Encrypted-Address Cache, ISCA 2019 ]]
   * [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?tok=6b0612&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fpage-overlays-for-fine-grained-memory-management_isca15.pdf | Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management, ISCA 2015. ]]   * [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?tok=6b0612&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fpage-overlays-for-fine-grained-memory-management_isca15.pdf | Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management, ISCA 2015. ]]
   * {{ 09152636.pdf | Plundervolt: Software-based Fault Injection Attacks against Intel SGX, IEEE Symposium on Security and Privacy 2020. }}   * {{ 09152636.pdf | Plundervolt: Software-based Fault Injection Attacks against Intel SGX, IEEE Symposium on Security and Privacy 2020. }}
papers.txt · Last modified: 2021/03/08 16:44 by alserm