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====== Papers ====== | ====== Papers ====== | ||
- | ===== Paper preferences (Due: 26 September 2020, 11:59 PM Zurich) ===== | + | ===== Paper preferences (Due: 6 March 2021, 11:59 PM Zurich) ===== |
Please check the list of papers below and then enter your preferences on the paper you would like to present during the seminar using the following link: | Please check the list of papers below and then enter your preferences on the paper you would like to present during the seminar using the following link: | ||
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===== Paper list ===== | ===== Paper list ===== | ||
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- | * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/ | + | * [[ https://www.pdl.cmu.edu/PDL-FTP/NVM/toggle-aware-compression-for-GPUs_hpca16.pdf | A |
- | * [[ https:// | + | * {{ 00898056.pdf | A |
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- | * [[ https://safari.ethz.ch/ | + | * [[ https://people.csail.mit.edu/sanchez/papers/2018.ams.micro.pdf | Adaptive |
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- | * [[ https://passat.crhc.illinois.edu/hpca19_cam.pdf | Architecting Waferscale Processors - A GPU Case Study, HPCA 2019 ]] | + | * [[ https://www.cs.virginia.edu/~smk9u/ |
- | * [[ https://pdfs.semanticscholar.org/66c3/661f86ca40fed69e683288b2106635fa5f37.pdf | Architecture of the IBM System/360, IBM Journal of Research and Development 1964. ]] | + | * [[ https://people.inf.ethz.ch/omutlu/pub/ |
- | * [[ https://people.inf.ethz.ch/omutlu/pub/ | + | * [[ https://arxiv.org/pdf/2102.05981.pdf | BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, HPCA 2021 ]] |
- | * [[ http://web.eecs.umich.edu/~zhengya/papers/chou_micro19.pdf | CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm, MICRO 2019 ]] | + | * {{ cape-hpca21.pdf | CAPE: |
+ | * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/ | ||
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- | * [[ https:// | + | * {{ 00566472.pdf | Custom-fit Processors: Letting Applications Define Architectures, MICRO 1996 }} |
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- | * [[ https://iacoma.cs.uiuc.edu/iacoma-papers/isca19_1.pdf | Designing Vertical Processors in Monolithic 3D, ISCA 2019 ]] | + | |
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+ | * [[ https://jianh.web.engr.illinois.edu/ | ||
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- | * [[ https://people.inf.ethz.ch/omutlu/pub/evanesco-secure-data-sanitization-for-flash-memory_asplos20.pdf | Evanesco: Architectural Support | + | * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/ |
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- | * [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php? | + | * [[ https://kilthub.cmu.edu/articles/Improving_DRAM_Performance_by_Parallelizing_Refreshes_with_Accesses/6468908/files/11897462.pdf | Improving DRAM Performance by Parallelizing Refreshes with Accesses, HPCA 2014 ]] |
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- | * [[ https://safari.ethz.ch/ | + | * [[ https://people.inf.ethz.ch/omutlu/pub/lisa-dram_hpca16.pdf | Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement |
- | * [[ https:// | + | * [[ https://www.cs.utexas.edu/users/witchel/pubs/mmp-asplos2002.pdf | Mondrian Memory Protection, ASPLOS 2002 ]] |
- | * [[ https://safari.ethz.ch/architecture_seminar/fall2020/lib/exe/ | + | |
* [[ http:// | * [[ http:// | ||
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- | * [[ https://safari.ethz.ch/architecture_seminar/spring2019/ | + | * [[ https://memlab.ece.gatech.edu/papers/ISCA_2019_1.pdf | New Attacks and Defense for Encrypted-Address |
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+ | * {{ 09152636.pdf | Plundervolt: | ||
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- | * [[ https://people.inf.ethz.ch/omutlu/pub/ | + | * [[ https://arxiv.org/pdf/2012.11890.pdf | SIMDRAM: A Framework for Bit-Serial SIMD Processing Using DRAM, ASPLOS 2021 ]] |
* [[ http:// | * [[ http:// | ||
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- | * [[ https://drkp.net/papers/latency-socc14.pdf | Tales of the Tail: Hardware, OS, and Application-level Sources of Tail Latency, SOCC 2014 ]] | + | * [[ https:// |
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+ | * [[ https://www.cis.upenn.edu/~milom/cis501-Fall09/ | ||
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- | * [[ https://safari.ethz.ch/architecture_seminar/ | + | * [[ https://www.eecs.harvard.edu/~dbrooks/reddi_hpca2009.pdf | Voltage Emergency Prediction: Using Signatures |
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- | * [[ https://people.inf.ethz.ch/omutlu/pub/ | + |
papers.1600798472.txt.gz · Last modified: 2021/02/05 08:35 (external edit)