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 ====== Papers ====== ====== Papers ======
  
-===== Paper preferences (Due: 26 September 2020, 11:59 PM Zurich) =====+===== Paper preferences (Due: 6 March 2021, 11:59 PM Zurich) =====
 Please check the list of papers below and then enter your preferences on the paper you would like to present during the seminar using the following link:  Please check the list of papers below and then enter your preferences on the paper you would like to present during the seminar using the following link: 
-  * [[ https://​moodle-app2.let.ethz.ch/​mod/​ratingallocate/​view.php?​id=488472 ​| Submit your preferences]]+  * [[ https://​moodle-app2.let.ethz.ch/​mod/​ratingallocate/​view.php?​id=566907 ​| Submit your preferences]]
  
 ===== Paper list ===== ===== Paper list =====
-  * [[ https://people.inf.ethz.ch/omutlu/pub/persistent-memory-management_weed13.pdf | A Case for Efficient Hardware-Software Cooperative Management of Storage and MemoryWEED 2013 ]]+  * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/​exe/​fetch.php?​tok=b927d2&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fbless_isca09.pdf | A Case for Bufferless Routing in On-Chip NetworksISCA 2009. ]]
   * [[ https://​www.pdl.cmu.edu/​PDL-FTP/​NVM/​ISCA39_SALP.pdf | A case for exploiting subarray-level parallelism (SALP) in DRAM, ISCA 2012. ]]   * [[ https://​www.pdl.cmu.edu/​PDL-FTP/​NVM/​ISCA39_SALP.pdf | A case for exploiting subarray-level parallelism (SALP) in DRAM, ISCA 2012. ]]
 +  * [[ https://​courses.engr.illinois.edu/​cs533/​sp2013/​reading_list/​8a.pdf | A Case for Intelligent RAM, MICRO 1997 ]]
   * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​tok=e8f2a6&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fqureshi_isca06.pdf | A Case for MLP-Aware Cache Replacement,​ ISCA 2006. ]]   * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​tok=e8f2a6&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fqureshi_isca06.pdf | A Case for MLP-Aware Cache Replacement,​ ISCA 2006. ]]
-  * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/​exe/​fetch.php?​tok=2bb676&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2FX-MEM_Expressive-Memory-for-Rich-Cross-Layer-Abstractions_isca18.pdf | A ​Case for Richer Cross-layer Abstractions:​ Bridging the Semantic Gap with Expressive MemoryISCA 2018. ]] +  * [[ https://www.pdl.cmu.edu/PDL-FTP/NVM/toggle-aware-compression-for-GPUs_hpca16.pdf | A ​case for toggle-aware compression for GPU systemsHPCA 2016 ]] 
-  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​ETC-memory-oversubscription-management-framework-for-GPUs_asplos19.pdf | A ​Framework for Memory Oversubscription Management in Graphics Processing UnitsASPLOS 2019. ]]+  * {{ 00898056.pdf | A ​Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data LocalityMICRO 2000 }}
   * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2020/​lib/​exe/​fetch.php?​media=05008902.pdf | A Logic-in-Memory Computer, IEEE Trans. Comput., 1970 ]]   * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2020/​lib/​exe/​fetch.php?​media=05008902.pdf | A Logic-in-Memory Computer, IEEE Trans. Comput., 1970 ]]
-  ​* [[ https://​www.nature.com/​articles/​s41467-020-15190-3 | A programmable chemical computer with memory and pattern recognition,​ Nature Communications,​ 2020 ]] +  * [[ https://​people.csail.mit.edu/sanchez/papers/2018.ams.micro.pdf | Adaptive ​Scheduling ​for Systems with Asymmetric Memory HierarchiesMICRO 2018 ]]
-  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​media=catapult.pdf | A reconfigurable fabric for accelerating large-scale datacenter services, ISCA 2014. ]] +
-  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=03719d&​media=https%3A%2F%2Fieeexplore.ieee.org%2Fiel7%2F7528194%2F7546461%2F07546493.pdf | A2:​ Analog malicious hardware, IEEE Symposium on Security and Privacy, 2016. ]] +
-  ​* [[ https://​people.inf.ethz.ch/omutlu/pub/in-memory-pointer-chasing-accelerator_iccd16.pdf | Accelerating Pointer Chasing in 3D-Stacked Memory: Challenges, Mechanisms, Evaluation, ICCD 2016. ]] +
-  * [[ https://​www.pdl.cmu.edu/​PDL-FTP/​NVM/​adaptive-latency-dram_hpca15.pdf | Adaptive-Latency DRAM: Optimizing DRAM Timing ​for the Common-CaseHPCA 2015 ]]+
   * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​tok=66e666&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fambit-bulk-bitwise-dram_micro17.pdf | Ambit:​ In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology, MICRO 2017. ]]   * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​tok=66e666&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fambit-bulk-bitwise-dram_micro17.pdf | Ambit:​ In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology, MICRO 2017. ]]
-  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=93568f&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fpcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM AlternativeISCA 2009. ]] +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​tok=bad8b0&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fbdi-compression_pact12.pdf | Base-Delta-Immediate Compression:​ Practical Data Compression for On-Chip CachesPACT 2012. ]] 
-  * [[ https://experts.illinois.edu/en/publications/architecting-waferscale-processors-a-gpu-case-study | Architecting Waferscale Processors ​A GPU Case StudyHPCA 2019 ]] +  * [[ https://www.cs.virginia.edu/~smk9u/CS6501F16/p153-gu.pdf | Biscuit:​ A Framework for Near-Data Processing of Big Data Workloads, ISCA 2016 ]] 
-  * [[ https://pdfs.semanticscholar.org/66c3/661f86ca40fed69e683288b2106635fa5f37.pdf | Architecture of the IBM System/360IBM Journal of Research and Development 1964. ]] +  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​BEER-bit-exact-ECC-recovery_micro20.pdf | Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention CharacteristicsMICRO 2020 ]] 
-  * [[ http://web.eecs.umich.edu/~zhengya/papers/chou_micro19.pdf | CASCADEConnecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing ParadigmMICRO 2019 ]]+  * [[ https://arxiv.org/pdf/2102.05981.pdf | BlockHammer:​ Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM RowsHPCA 2021 ]] 
 +  * {{ cape-hpca21.pdf | CAPE:​ A Content-Addressable Processing Engine, HPCA 2021 }} 
 +  * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/​exe/​fetch.php?​tok=1f090d&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fchipper_hpca11.pdf | CHIPPERA Low-Complexity Bufferless Deflection RouterHPCA 2011. ]]
   * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​CLR-DRAM_capacity-latency-reconfigurable-DRAM_isca20.pdf | CLR-DRAM:​ A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off, ISCA 2020. ]]   * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​CLR-DRAM_capacity-latency-reconfigurable-DRAM_isca20.pdf | CLR-DRAM:​ A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off, ISCA 2020. ]]
 +  * [[ https://​people.ucsc.edu/​~hlitz/​papers/​asplos2020.pdf | Classifying memory access patterns for prefetching,​ ASPLOS 2020 ]]
 +  * [[ https://​dl.acm.org/​doi/​pdf/​10.1145/​285930.285974?​casa_token=5EnBI-YqPtsAAAAA%3A3U5ZOafYDoMIILhGg8ykpIS4O-vx4dkrNGHP4UD4yCi8VH-nC3rgGEK5QNAg3-fVHmc452R809CNkg | Computer structures: What have we learned from the PDP-11?, ISCA 1976 ]]
 +  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​CONDA-coherence-for-near-data-accelerators_isca19.pdf | CoNDA:​ Efficient Cache Coherence Support for Near-Data Accelerators ]]
   * [[ https://​parallel.princeton.edu/​papers/​micro19-gao.pdf | ComputeDRAM:​ In-Memory Compute Using Off-the-Shelf DRAMs, MICRO 2019 ]]   * [[ https://​parallel.princeton.edu/​papers/​micro19-gao.pdf | ComputeDRAM:​ In-Memory Compute Using Off-the-Shelf DRAMs, MICRO 2019 ]]
-  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​continuous-runahead-engine_micro16.pdf | Continuous RunaheadTransparent Hardware Acceleration for Memory Intensive Workloads, MICRO 2016 ]] +  * {{ 00566472.pdf | Custom-fit ProcessorsLetting Applications Define Architectures, MICRO 1996 }}
-  * [[ http://​people.ece.cornell.edu/​martinez/​doc/​isca07.pdf | Core Fusion: Accommodating Software Diversity in Chip Multiprocessors,​ ISCA 2007 ]]+
   * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=388edc&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fdrange-dram-latency-based-true-random-number-generator_hpca19.pdf | D-RaNGe:​ Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput, HPCA 2019. ]]   * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=388edc&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fdrange-dram-latency-based-true-random-number-generator_hpca19.pdf | D-RaNGe:​ Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput, HPCA 2019. ]]
-  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​tok=edb7f1&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fflash-memory-data-retention_hpca15.pdf | Data Retention in MLC NAND Flash MemoryCharacterizationOptimization ​and RecoveryHPCA 2015. ]] +  ​* [[ https://​hps.ece.utexas.edu/​pub/​lin_micro18.pdf | Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts via Data Duplication,​ MICRO 2018 ]] 
-  * [[ https://iacoma.cs.uiuc.edu/iacoma-papers/isca19_1.pdf | Designing Vertical Processors in Monolithic 3DISCA 2019 ]]+  ​* [[ https://​safari.ethz.ch/​architecture_seminar/​fall2020/​lib/​exe/​fetch.php?​media=3123939.3123977.pdf | DRISA:​ A DRAM-based Reconfigurable In-Situ Accelerator,​ MICRO 2017 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=602468&​media=https%3A%2F%2Farxiv.org%2Fpdf%2F1510.00149.pdf | Deep CompressionCompressing Deep Neural Network with PruningTrained Quantization ​and Huffman CodingArXiv 2016. ]] 
 +  * [[ https://jianh.web.engr.illinois.edu/​papers/​deepstore.pdf | DeepStore: In-Storage Acceleration for Intelligent QueriesMICRO 2019 ]]
   * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​media=diva99.pdf | DIVA:​ A Reliable Substrate for Deep Submicron Microarchitecture Design, MICRO 1999. ]]   * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​media=diva99.pdf | DIVA:​ A Reliable Substrate for Deep Submicron Microarchitecture Design, MICRO 1999. ]]
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​media=perceptron_branch_predictor.pdf | Dynamic branch prediction with perceptrons,​ HPCA 2001. ]]
   * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​EDEN-efficient-DNN-inference-with-approximate-memory_micro19.pdf | EDEN:​ Enabling Energy-Efficient,​ High-Performance Deep Neural Network Inference Using Approximate DRAM, MICRO 2019 ]]   * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​EDEN-efficient-DNN-inference-with-approximate-memory_micro19.pdf | EDEN:​ Enabling Energy-Efficient,​ High-Performance Deep Neural Network Inference Using Approximate DRAM, MICRO 2019 ]]
-  * [[ https://people.inf.ethz.ch/omutlu/pub/evanesco-secure-data-sanitization-for-flash-memory_asplos20.pdf | EvanescoArchitectural Support ​for Efficient Data Sanitization in Modern Flash-Based Storage ​Systems, ASPLOS ​2020. ]] +  * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/​exe/​fetch.php?​tok=468976&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Ffst_asplos10.pdf | Fairness via Source ThrottlingA Configurable and High-Performance Fairness Substrate ​for Multi-Core Memory ​Systems, ASPLOS ​2010. ]] 
-  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​hamm_isca09.pdf | Flexible Reference Counting-Based Hardware Acceleration for Garbage CollectionISCA 2009 ]]+  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​FIGARO-fine-grained-in-DRAM-data-relocation-and-caching_micro20.pdf | FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and CachingMICRO 2020 ]]
   * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=527fea&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fdram-row-hammer_isca14.pdf | Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, ISCA 2014. ]]   * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=527fea&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fdram-row-hammer_isca14.pdf | Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, ISCA 2014. ]]
   * [[ https://​arxiv.org/​pdf/​2009.07692.pdf | GenASM:​ A High-Performance,​ Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis, MICRO 2020 ]]   * [[ https://​arxiv.org/​pdf/​2009.07692.pdf | GenASM:​ A High-Performance,​ Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis, MICRO 2020 ]]
-  * [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?​tok=d2103c&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2FGoogle-consumer-workloads-data-movement-and-PIM_asplos18.pdf | Google Workloads for Consumer Devices: Mitigating Data Movement BottlenecksASPLOS 2018. ]] +  * [[ https://kilthub.cmu.edu/articles/Improving_DRAM_Performance_by_Parallelizing_Refreshes_with_Accesses/6468908/files/11897462.pdf | Improving DRAM Performance by Parallelizing Refreshes with AccessesHPCA 2014 ]]
-  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2020/​lib/​exe/​fetch.php?​media=3307650.3322275.pdf | GraphSSD:​ Graph Semantics Aware SSD, ISCA, 2019 ]] +
-  * [[ https://​www.iscaconf.org/​isca2020/​papers/​466100a391.pdf | Hardware-Software Co-Design for Brain-Computer Interfaces, ISCA, 2020 ]] +
-  * [[ https://​conferences.computer.org/​isca/​pdfs/​ISCA2020-4QlDegUf3fKiwUXfV0KdCm/​466100a846/​466100a846.pdf | Hyper-AP:​ Enhancing Associative Processing Through a Full-Stack Optimization,​ ISCA 2020. ]]+
   * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=4be535&​media=http%3A%2F%2Fwww.cs.utah.edu%2F~rajeev%2Fpubs%2Fisca16-old.pdf | ISAAC:​ A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars, ISCA 2016. ]]   * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=4be535&​media=http%3A%2F%2Fwww.cs.utah.edu%2F~rajeev%2Fpubs%2Fisca16-old.pdf | ISAAC:​ A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars, ISCA 2016. ]]
   * [[ https://​www.isis.vanderbilt.edu/​sites/​default/​files/​radar.pdf | Leveraging EM Side-Channel Information to Detect Rowhammer Attacks, IEEE Symposium on Security and Privacy, 2020 ]]   * [[ https://​www.isis.vanderbilt.edu/​sites/​default/​files/​radar.pdf | Leveraging EM Side-Channel Information to Detect Rowhammer Attacks, IEEE Symposium on Security and Privacy, 2020 ]]
-  * [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/​exe/​fetch.php?​tok=d81f5d&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fmph_usenix_security07.pdf | Memory Performance AttacksDenial of Memory Service ​in Multi-Core SystemsUSENIX SECURITY 2007. ]] +  * [[ https://people.inf.ethz.ch/omutlu/pub/lisa-dram_hpca16.pdf | Low-Cost Inter-Linked Subarrays (LISA)Enabling Fast Inter-Subarray Data Movement ​in DRAMHPCA 2016 ]] 
-  * [[ https://safari.ethz.ch/architecture_seminar/fall2020/lib/exe/​fetch.php?​media=07446049.pdf | Memristive Boltzmann machine: A hardware accelerator for combinatorial optimization and deep learningHPCA 2016 ]]+  * [[ https://www.cs.utexas.edu/users/witchel/pubs/mmp-asplos2002.pdf | Mondrian Memory ProtectionASPLOS 2002 ]]
   * [[ http://​cccp.eecs.umich.edu/​papers/​shrupad-micro17.pdf | Mirage cores: the illusion of many out-of-order cores using in-order hardware, MICRO 2017 ]]   * [[ http://​cccp.eecs.umich.edu/​papers/​shrupad-micro17.pdf | Mirage cores: the illusion of many out-of-order cores using in-order hardware, MICRO 2017 ]]
-  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​media=morphcore.pdf | MorphCore:​ An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP, MICRO 2012. ]] 
   * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​media=10.1.1.20.8558.pdf | Multiscalar Processors, ISCA 1995. ]]   * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​media=10.1.1.20.8558.pdf | Multiscalar Processors, ISCA 1995. ]]
-  * [[ https://safari.ethz.ch/architecture_seminar/spring2019/​lib/​exe/​fetch.php?​tok=d310e0&​media=https%3A%2F%2Farxiv.org%2Fpdf%2F1805.03718.pdf | Neural Cache: Bit-Serial In-Cache ​Acceleration of Deep Neural Networks, ISCA 2018. ]] +  * [[ https://memlab.ece.gatech.edu/papers/ISCA_2019_1.pdf | New Attacks and Defense for Encrypted-Address ​Cache, ISCA 2019 ]]
-  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​hwbugs_micro08.pdf | Online Design Bug Detection: RTL Analysis, Flexible Mechanisms, and Evaluation, MICRO, 2008 ]] +
-  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2020/​lib/​exe/​fetch.php?​media=3307650.3322212.pdf | Opportunistic Computing in GPU Architectures, ISCA'19 ]]+
   * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=6b0612&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fpage-overlays-for-fine-grained-memory-management_isca15.pdf | Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management, ISCA 2015. ]]   * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=6b0612&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fpage-overlays-for-fine-grained-memory-management_isca15.pdf | Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management, ISCA 2015. ]]
-  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=f31abc&media=http%3A%2F%2Fcccp.eecs.umich.edu%2Fpapers%2Fntclark-micro03.pdf | Processor acceleration through automated instruction set customizationMICRO 2003. ]]+  ​* {{ 09152636.pdf | Plundervolt:​ Software-based Fault Injection Attacks against Intel SGX, IEEE Symposium on Security and Privacy 2020. }} 
 +  * [[ https://​par.nsf.gov/​servlets/​purl/​10047786 | Parallel Automata Processor, ISCA 2007 ]] 
 +  ​* [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=476ab4&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fpim-enabled-instructons-for-low-overhead-pim_isca15.pdf | PIM-Enabled Instructions:​ A Low-OverheadLocality-Aware Processing-in-Memory Architecture,​ ISCA, 2015. ]] 
 +  * [[ http://​tnm.engin.umich.edu/​wp-content/​uploads/​sites/​353/​2021/​01/​2021.02.Prodigy_HPCA2021_Camera_Ready.pdf | Prodigy:​ Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design, HPCA 2021 ]]
   * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=8d2c6c&​media=https%3A%2F%2Fstatic.googleusercontent.com%2Fmedia%2Fresearch.google.com%2Fen%2F%2Fpubs%2Farchive%2F44271.pdf | Profiling a Warehouse-scale Computer, ISCA, 2015. ]]   * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=8d2c6c&​media=https%3A%2F%2Fstatic.googleusercontent.com%2Fmedia%2Fresearch.google.com%2Fen%2F%2Fpubs%2Farchive%2F44271.pdf | Profiling a Warehouse-scale Computer, ISCA, 2015. ]]
-  * [[ https://​rambleed.com/​docs/​20190603-rambleed-web.pdf | RAMBleed:​ Reading Bits in Memory Without Accessing Them, IEEE Symposium on Security and Privacy, 2020. ]] 
   * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​media=10.1.1.331.8266.pdf | Razor:​ A Low-Power Pipeline Based on Circuit-Level Timing Speculation,​ MICRO 2003. ]]   * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​media=10.1.1.331.8266.pdf | Razor:​ A Low-Power Pipeline Based on Circuit-Level Timing Speculation,​ MICRO 2003. ]]
 +  * [[ https://​arxiv.org/​pdf/​2012.12178.pdf | Reducing Solid-state Drive Read Latency by Optimizing Read-retry, ASPLOS 2021 ]]
   * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​Revisiting-RowHammer_isca20.pdf | Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques, ISCA 2020. ]]   * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​Revisiting-RowHammer_isca20.pdf | Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques, ISCA 2020. ]]
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​tok=7ebf70&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fmutlu_hpca03.pdf | Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors, HPCA 2003. ]]
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papers.1600783020.txt.gz · Last modified: 2021/02/05 09:35 (external edit)