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 ====== Papers ====== ====== Papers ======
  
-We will announce ​the paper list as soon as possible ​and allow the students ​to enter their preferences for their papers of choice.+===== Paper preferences (Due: 6 March 2021, 11:59 PM Zurich) ===== 
 +Please check the list of papers below and then enter your preferences on the paper you would like to present during the seminar using the following link:  
 +  * [[ https://​moodle-app2.let.ethz.ch/​mod/​ratingallocate/​view.php?​id=566907 | Submit your preferences]] 
 + 
 +===== Paper list ===== 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​tok=b927d2&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fbless_isca09.pdf | A Case for Bufferless Routing in On-Chip Networks, ISCA 2009. ]] 
 +  * [[ https://​www.pdl.cmu.edu/​PDL-FTP/​NVM/​ISCA39_SALP.pdf | A case for exploiting subarray-level parallelism (SALP) in DRAM, ISCA 2012. ]] 
 +  * [[ https://​courses.engr.illinois.edu/​cs533/​sp2013/​reading_list/​8a.pdf | A Case for Intelligent RAM, MICRO 1997 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​tok=e8f2a6&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fqureshi_isca06.pdf | A Case for MLP-Aware Cache Replacement,​ ISCA 2006. ]] 
 +  * [[ https://​www.pdl.cmu.edu/​PDL-FTP/​NVM/​toggle-aware-compression-for-GPUs_hpca16.pdf | A case for toggle-aware compression for GPU systems, HPCA 2016 ]] 
 +  * {{ 00898056.pdf | A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data Locality, MICRO 2000 }} 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2020/​lib/​exe/​fetch.php?​media=05008902.pdf | A Logic-in-Memory Computer, IEEE Trans. Comput., 1970 ]] 
 +  * [[ https://​people.csail.mit.edu/​sanchez/​papers/​2018.ams.micro.pdf | Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies,​ MICRO 2018 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​tok=66e666&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fambit-bulk-bitwise-dram_micro17.pdf | Ambit:​ In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology, MICRO 2017. ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​tok=bad8b0&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fbdi-compression_pact12.pdf | Base-Delta-Immediate Compression:​ Practical Data Compression for On-Chip Caches, PACT 2012. ]] 
 +  * [[ https://​www.cs.virginia.edu/​~smk9u/​CS6501F16/​p153-gu.pdf | Biscuit:​ A Framework for Near-Data Processing ​of Big Data Workloads, ISCA 2016 ]] 
 +  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​BEER-bit-exact-ECC-recovery_micro20.pdf | Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics,​ MICRO 2020 ]] 
 +  * [[ https://​arxiv.org/​pdf/​2102.05981.pdf | BlockHammer:​ Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, HPCA 2021 ]] 
 +  * {{ cape-hpca21.pdf | CAPE:​ A Content-Addressable Processing Engine, HPCA 2021 }} 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​tok=1f090d&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fchipper_hpca11.pdf | CHIPPER:​ A Low-Complexity Bufferless Deflection Router, HPCA 2011. ]] 
 +  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​CLR-DRAM_capacity-latency-reconfigurable-DRAM_isca20.pdf | CLR-DRAM:​ A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off, ISCA 2020. ]] 
 +  * [[ https://​people.ucsc.edu/​~hlitz/​papers/​asplos2020.pdf | Classifying memory access patterns for prefetching,​ ASPLOS 2020 ]] 
 +  * [[ https://​dl.acm.org/​doi/​pdf/​10.1145/​285930.285974?​casa_token=5EnBI-YqPtsAAAAA%3A3U5ZOafYDoMIILhGg8ykpIS4O-vx4dkrNGHP4UD4yCi8VH-nC3rgGEK5QNAg3-fVHmc452R809CNkg | Computer structures: What have we learned from the PDP-11?, ISCA 1976 ]] 
 +  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​CONDA-coherence-for-near-data-accelerators_isca19.pdf | CoNDA:​ Efficient Cache Coherence Support for Near-Data Accelerators ]] 
 +  * [[ https://​parallel.princeton.edu/​papers/​micro19-gao.pdf | ComputeDRAM:​ In-Memory Compute Using Off-the-Shelf DRAMs, MICRO 2019 ]] 
 +  * {{ 00566472.pdf | Custom-fit Processors: Letting Applications Define Architectures,​ MICRO 1996 }} 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=388edc&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fdrange-dram-latency-based-true-random-number-generator_hpca19.pdf | D-RaNGe:​ Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput, HPCA 2019. ]] 
 +  * [[ https://​hps.ece.utexas.edu/​pub/​lin_micro18.pdf | Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts via Data Duplication,​ MICRO 2018 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2020/​lib/​exe/​fetch.php?​media=3123939.3123977.pdf | DRISA:​ A DRAM-based Reconfigurable In-Situ Accelerator,​ MICRO 2017 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=602468&​media=https%3A%2F%2Farxiv.org%2Fpdf%2F1510.00149.pdf | Deep Compression:​ Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding, ArXiv 2016. ]] 
 +  * [[ https://​jianh.web.engr.illinois.edu/​papers/​deepstore.pdf | DeepStore:​ In-Storage Acceleration for Intelligent Queries, MICRO 2019 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​media=diva99.pdf | DIVA:​ A Reliable Substrate for Deep Submicron Microarchitecture Design, MICRO 1999. ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​media=perceptron_branch_predictor.pdf | Dynamic branch prediction with perceptrons,​ HPCA 2001. ]] 
 +  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​EDEN-efficient-DNN-inference-with-approximate-memory_micro19.pdf | EDEN:​ Enabling Energy-Efficient,​ High-Performance Deep Neural Network Inference Using Approximate DRAM, MICRO 2019 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​tok=468976&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Ffst_asplos10.pdf | Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems, ASPLOS 2010. ]] 
 +  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​FIGARO-fine-grained-in-DRAM-data-relocation-and-caching_micro20.pdf | FIGARO:​ Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching, MICRO 2020 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=527fea&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fdram-row-hammer_isca14.pdf | Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, ISCA 2014. ]] 
 +  * [[ https://​arxiv.org/​pdf/​2009.07692.pdf | GenASM:​ A High-Performance,​ Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis, MICRO 2020 ]] 
 +  * [[ https://​kilthub.cmu.edu/​articles/​Improving_DRAM_Performance_by_Parallelizing_Refreshes_with_Accesses/​6468908/​files/​11897462.pdf | Improving DRAM Performance by Parallelizing Refreshes with Accesses, HPCA 2014 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=4be535&​media=http%3A%2F%2Fwww.cs.utah.edu%2F~rajeev%2Fpubs%2Fisca16-old.pdf | ISAAC:​ A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars, ISCA 2016. ]] 
 +  * [[ https://​www.isis.vanderbilt.edu/​sites/​default/​files/​radar.pdf | Leveraging EM Side-Channel Information to Detect Rowhammer Attacks, IEEE Symposium on Security and Privacy, 2020 ]] 
 +  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​lisa-dram_hpca16.pdf | Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM, HPCA 2016 ]] 
 +  * [[ https://​www.cs.utexas.edu/​users/​witchel/​pubs/​mmp-asplos2002.pdf | Mondrian Memory Protection, ASPLOS 2002 ]] 
 +  * [[ http://​cccp.eecs.umich.edu/​papers/​shrupad-micro17.pdf | Mirage cores: the illusion of many out-of-order cores using in-order hardware, MICRO 2017 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​media=10.1.1.20.8558.pdf | Multiscalar Processors, ISCA 1995. ]] 
 +  * [[ https://​memlab.ece.gatech.edu/​papers/​ISCA_2019_1.pdf | New Attacks and Defense for Encrypted-Address Cache, ISCA 2019 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=6b0612&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fpage-overlays-for-fine-grained-memory-management_isca15.pdf | Page Overlays: An Enhanced Virtual Memory Framework to Enable Fine-grained Memory Management, ISCA 2015. ]] 
 +  * {{ 09152636.pdf | Plundervolt:​ Software-based Fault Injection Attacks against Intel SGX, IEEE Symposium on Security and Privacy 2020. }} 
 +  * [[ https://​par.nsf.gov/​servlets/​purl/​10047786 | Parallel Automata Processor, ISCA 2007 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=476ab4&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fpim-enabled-instructons-for-low-overhead-pim_isca15.pdf | PIM-Enabled Instructions:​ A Low-Overhead,​ Locality-Aware Processing-in-Memory Architecture,​ ISCA, 2015. ]] 
 +  * [[ http://​tnm.engin.umich.edu/​wp-content/​uploads/​sites/​353/​2021/​01/​2021.02.Prodigy_HPCA2021_Camera_Ready.pdf | Prodigy:​ Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design, HPCA 2021 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=8d2c6c&​media=https%3A%2F%2Fstatic.googleusercontent.com%2Fmedia%2Fresearch.google.com%2Fen%2F%2Fpubs%2Farchive%2F44271.pdf | Profiling a Warehouse-scale Computer, ISCA, 2015. ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​media=10.1.1.331.8266.pdf | Razor:​ A Low-Power Pipeline Based on Circuit-Level Timing Speculation,​ MICRO 2003. ]] 
 +  * [[ https://​arxiv.org/​pdf/​2012.12178.pdf | Reducing Solid-state Drive Read Latency by Optimizing Read-retry, ASPLOS 2021 ]] 
 +  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​Revisiting-RowHammer_isca20.pdf | Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques, ISCA 2020. ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​tok=7ebf70&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fmutlu_hpca03.pdf | Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors, HPCA 2003. ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=5d56bf&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Frlmc_isca08.pdf | Self Optimizing Memory Controllers:​ A Reinforcement Learning Approach, ISCA 2008. ]] 
 +  * [[ https://​arxiv.org/​pdf/​2012.11890.pdf | SIMDRAM:​ A Framework for Bit-Serial SIMD Processing Using DRAM, ASPLOS 2021 ]] 
 +  * [[ http://​course.ece.cmu.edu/​~ece447/​s12/​lib/​exe/​fetch.php?​media=wiki:​chappell-isca1999.pdf | Simultaneous Subordinate Microthreading (SSMT), ISCA 1999. ]] 
 +  * [[ http://​www.cse.zju.edu.cn/​eclass/​attachments/​2017-10/​01-1508214936-262120.pdf | Single-chip microprocessor that communicates directly using light, Nature 2015 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​media=10.1.1.36.8249.pdf | Slipstream processors: Improving both performance and fault tolerance, ASPLOS 2000. ]] 
 +  * [[ https://​arxiv.org/​pdf/​1910.09020.pdf | SneakySnake:​ A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs, Bioinformatics 2020 ]] 
 +  * [[ https://​spectreattack.com/​spectre.pdf | Spectre Attacks: Exploiting Speculative Execution, IEEE Symposium on Security and Privacy 2019 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​fall2018/​lib/​exe/​fetch.php?​media=p294-rajwar.pdf | Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution, MICRO 2001. ]] 
 +  * [[ https://​www.cs.tau.ac.il/​~mad/​publications/​micro2019-stt.pdf | Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data, MICRO 2019 ]] 
 +  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​SynCron-synchronization-for-near-data-processing-systems_hpca21.pdf | SynCron:​ Efficient Synchronization Support for Near-Data-Processing Architectures,​ HPCA 2021 ]] 
 +  * [[ https://​www.cis.upenn.edu/​~milom/​cis501-Fall09/​papers/​Alpha21264.pdf | The Alpha 21264 Microprocessor,​ IEEE Micro 1999 ]] 
 +  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​dirty-block-index_isca14.pdf | The Dirty-Block Index, ISCA 2014 ]] 
 +  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​LocalityDescriptor-Cross-Layer-GPU-Data-Locality-Abstraction_isca18.pdf | The Locality Descriptor: A Holistic Cross-Layer Abstraction to Express Data Locality in GPUs, ISCA 2018 ]] 
 +  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​VBI-virtual-block-interface_isca20.pdf | The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework, ISCA, 2020 ]] 
 +  * [[ http://​www.eecs.harvard.edu/​~htk/​publication/​1987-ieee-toc-annaratone-arnould-gross-kung-lam-menzilcioglu-webb.pdf | The Warp Computer: Architecture,​ Implementation,​ and Performance,​ IEEE TC 1987 ]] 
 +  * [[ https://​safari.ethz.ch/​architecture_seminar/​spring2019/​lib/​exe/​fetch.php?​tok=873601&​media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Ftldram_hpca13.pdf | Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,​ HPCA 2013. ]] 
 +  * [[ https://​people.inf.ethz.ch/​omutlu/​pub/​rowhammer-TRRespass_ieee_security_privacy20.pdf | TRRespass:​ Exploiting the Many Sides of Target Row Refresh, IEEE Symposium on Security and Privacy, 2020 ]] 
 +  * [[ https://​people.eecs.berkeley.edu/​~kubitron/​courses/​cs252-F00/​handouts/​papers/​p263-fisher.pdf | Very Long Instruction Word Architectures and the ELI-512, ISCA 1983 ]] 
 +  * [[ https://​www.eecs.harvard.edu/​~dbrooks/​reddi_hpca2009.pdf | Voltage Emergency Prediction: Using Signatures to Reduce Operating Margins, HPCA 2009 ]]
papers.1614162204.txt.gz · Last modified: 2021/02/24 11:23 by alserm