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readings [2021/04/21 15:32] rahberareadings [2021/06/03 17:10] (current) – [Session 6 (06.05 Thu.)] hluo
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   * {{ https://arxiv.org/pdf/1912.08735.pdf | Jeremie S. Kim, Can Firtina, Damla Senol Cali, Mohammed Alser, Nastaran Hajinazar, Can Alkan, and Onur Mutlu, "AirLift: A Fast and Comprehensive Technique for Translating Alignments between Reference Genomes," arXiv 2019 https://arxiv.org/abs/1912.08735.}}   * {{ https://arxiv.org/pdf/1912.08735.pdf | Jeremie S. Kim, Can Firtina, Damla Senol Cali, Mohammed Alser, Nastaran Hajinazar, Can Alkan, and Onur Mutlu, "AirLift: A Fast and Comprehensive Technique for Translating Alignments between Reference Genomes," arXiv 2019 https://arxiv.org/abs/1912.08735.}}
  
-===== Lecture 5 (25.03 Thu.) =====+===== Session 1 (25.03 Thu.) =====
  
-=== Described (Lecture 5) ===+=== Mentioned (session 1) ===
   * {{ https://arxiv.org/abs/2004.02354 | Wang, Minghua, et al. "DRAMDig: a knowledge-assisted tool to uncover DRAM address mapping."2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020.}}   * {{ https://arxiv.org/abs/2004.02354 | Wang, Minghua, et al. "DRAMDig: a knowledge-assisted tool to uncover DRAM address mapping."2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020.}}
   * {{ https://users.ece.cmu.edu/~yoonguk/papers/kim-isca14.pdf| Yoongu Kim, Ross Daly, Jeremie S. Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu, "Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors", ISCA 2014}}   * {{ https://users.ece.cmu.edu/~yoonguk/papers/kim-isca14.pdf| Yoongu Kim, Ross Daly, Jeremie S. Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu, "Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors", ISCA 2014}}
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 Making DRAM Stronger Against Row Hammering" DAC 2017 }} Making DRAM Stronger Against Row Hammering" DAC 2017 }}
   *{{ graphene.pdf | Y. Park, W. Kwon, E. Lee, T. J. Ham, J. Ho Ahn and J. W. Lee | "Graphene: Strong yet Lightweight Row Hammer Protection," MICRO 2020 }}   *{{ graphene.pdf | Y. Park, W. Kwon, E. Lee, T. J. Ham, J. Ho Ahn and J. W. Lee | "Graphene: Strong yet Lightweight Row Hammer Protection," MICRO 2020 }}
 +
 +===== Session 2 (01.04 Thu.) =====
 +
 +=== Mentioned (Session 2) ===
 +  * {{ https://people.inf.ethz.ch/omutlu/pub/lisa-dram_hpca16.pdf | Kevin K. Chang, Prashant J. Nair, Donghyuk Lee, Saugata Ghose, Moinuddin K. Qureshi, and Onur Mutlu, "Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM", in HPCA, 2016}}
 +
  
 ===== Session 3 (15.04 Thu.) ===== ===== Session 3 (15.04 Thu.) =====
  
-=== Described (Session 3) ===+=== Mentioned (Session 3) === 
 +  * {{ https://ramyadhadidi.github.io/files/a48-hadidi.pdf | Ramyad Hadidi, Lifeng Nai, Hyojong Kim, and Hyesoon Kim, "CAIRO: A Compiler-Assisted Technique for Enabling Instruction-Level Offloading of Processing-In-Memory", in TACO, 2017}} 
 +  * {{GraphPIM.pdf | L. Nai, R. Hadidi, J. Sim, H. Kim, P. Kumar and H. Kim, "GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks", in HPCA, 2017}} 
 +  * {{https://adwaitjog.github.io/docs/pdf/ndc-isca19.pdf | A. Pattnaik et al., "Opportunistic Computing in GPU Architectures," in ISCA, 2019}} 
 + 
 + 
 +===== Session 4 (22.04 Thu.) ===== 
 + 
 +=== Mentioned (Session 4.1) === 
 +  * {{ https://people.inf.ethz.ch/omutlu/pub/onchip-network-congestion-scalability_sigcomm2012.pdf | George Nychis, Chris Fallin, Thomas Moscibroda, and Onur Mutlu, "On-chip networks from a networking perspective: congestion and scalability in many-core interconnects", in SIGCOMM, 2012}} 
 +  * {{ https://people.inf.ethz.ch/omutlu/pub/chipper_hpca11.pdf | Chris Fallin, Chris Craik, and Onur Mutlu, "CHIPPER: A low-complexity bufferless deflection router", in HPCA, 2011}} 
 + 
 +=== Mentioned (Session 4.2) === 
 +  * {{ manticore.pdf | Zaruba Florian, Fabian Schuiki, and Luca Benini, "Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing", in IEEE Mirco, 2020}} 
 +  * {{ isc2016.pdf | Ainsworth Sam, and Timothy M. Jones, "Graph Prefetching Using Data Structure Knowledge", in ICS, 2016}} 
 +  * {{ micro19.pdf | Dadu Vidushi, Jian Weng, Sihao Liu, and Tony Nowatzki., "Towards General Purpose Acceleration by Exploiting Common Data-Dependence Forms", in MICRO, 2019}} 
 +  * {{ pact14.pdf | Kumar Snehasish, Arrvindh Shriraman, Vijayalakshmi Srinivasan, Dan Lin, and Jordon Phillips, "SQRL: hardware accelerator for collecting software data structures", in PACT, 2014}} 
 +  * {{ isca99.pdf | Roth Amir, and Gurindar S. Sohi, "Effective jump-pointer prefetching for linked data structures", in ISCA, 1999}} 
 + 
 +===== Session 5 (29.04 Thu.) ===== 
 + 
 +=== Mentioned (Session 5.1) === 
 +  * {{ exynos.pdf | Brian Grayson, Jeff Rupley, Gerald Zuraski Jr., Eric Quinnell, Daniel A. Jimenez, Tarun Nakra, 
 +Paul Kitchin, Ryan Hensley, Edward Brekelbaum, Vikas Sinha, and Ankit Ghiya, "Evolution of the Samsung Exynos CPU Microarchitecture", in ISCA, 2020}} 
 +  * {{ history.pdf | Andre Seznec, "Analysis of the O-GEometric History Length branch predictor", in ISCA, 2005}} 
 + 
 + 
 +=== Mentioned (Session 5.2) === 
 +  * {{ morse.pdf | Janani Mukundan, and Jose F. Martinez, "MORSE: Multi-objective Reconfigurable 
 +Self-optimizing Memory Scheduler", in HPCA, 2012}} 
 +  * {{ http://incompleteideas.net/book/RLbook2020.pdf | Richard S. Sutton 
 +and Andrew G. Barto, "Reinforcement Learning: An Introduction", MIT Press, 2018}} 
 + 
 + 
 +===== Session 6 (06.05 Thu.) ===== 
 + 
 +=== Mentioned (Session 6.1) === 
 +  * {{ approximationwithdnns.pdf | Csáji et al., Approximation with Artificial Neural Networks, PSU 2001}} 
 +  * {{ imagenet-classification-with-deep-convolutional-nn.pdf | Krizhevsky, Alex, Ilya Sutskever, and Geoffrey E. Hinton. "Imagenet classification with deep convolutional neural networks." Advances in neural information processing systems 25 (2012): 1097-1105}} 
 +  * {{verydnn.pdf | Simonyan, Karen, and Andrew Zisserman. "Very deep convolutional networks for large-scale image recognition." arXiv preprint arXiv:1409.1556 (2014) }} 
 +  * {{surveydnncompression.pdf | Cheng, Yu, et al. "A survey of model compression and acceleration for deep neural networks." arXiv preprint arXiv:1710.09282 (2017)}} 
 +  * {{predictingdnn.pdf | Denil, Misha, et al. "Predicting parameters in deep learning." arXiv preprint arXiv:1306.0543 (2013)}} 
 +  * {{ xu-mannor2012_article_robustnessandgeneralization.pdf | Xu, Huan, and Shie Mannor. "Robustness and generalization." Machine learning 86.3 (2012): 391-423}} 
 +  * {{robustness_and_or_redundancy_emerge_in_overparametrized_deep_neural_networks.pdf | Casper, Stephen, et al. "Robustness and/or Redundancy Emerge in Overparametrized Deep Neural Networks." (2019)}} 
 +  * {{sparsednn.pdf | Guo, Yiwen, et al. "Sparse dnns with improved adversarial robustness." arXiv preprint arXiv:1810.09619 (2018)}} 
 + 
 + 
 +=== Mentioned (Session 6.2) === 
 +  * {{ alser-seminar-in-comparch-2021-lecture4-gatekeeper-afterlecture.pdf | Alser, Mohammed, et al. "GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping." Bioinformatics 33.21 (2017): 3355-3363}} 
 +  * {{ s41598-019-41228-8.pdf | Takahashi, Christopher N., et al. "Demonstration of end-to-end automation of DNA data storage." Scientific reports 9.1 (2019): 1-5}} 
 +  * {{1412.0348.pdf | Backurs, Arturs, and Piotr Indyk. "Edit distance cannot be computed in strongly subquadratic time (unless SETH is false)." Proceedings of the forty-seventh annual ACM symposium on Theory of computing. 2015 }} 
 +  * {{ genasm.pdf | Cali, Damla Senol, et al. "GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis." 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2020 }}
  
-=== Suggested (Session 3)===+=== Mentioned (Session 9) === 
 +  * {{ tldram_hpca13.pdf | D. Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture”, in  HPCA 2013 }} 
 +  * {{ charm_isca13.pdf | Y. H. Son et al., “Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations,” in ISCA 2013 }} 
 +  * {{ das_micro15.pdf | S. L. Lu et al., “Improving DRAM Latency with Dynamic Asymmetric Subarray,” in MICRO 2015 }} 
 +  * {{ lisa-dram_hpca16.pdf | K. K. Chang et al., “Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM, “ in HPCA 2016 }}
readings.1619019162.txt.gz · Last modified: 2021/04/21 15:32 by rahbera