readings
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Table of Contents
Readings
Lecture 1 (25.02 Thu.)
Suggested (lecture 1):
Mentioned in Lecture 1:
Lecture 2 (04.03 Thu.)
Suggested (lecture 2):
Lecture 3 (11.03 Thu.)
Suggested (lecture 3):
Lecture 4 (18.03 Thu.)
Suggested (lecture 4):
Described in detail during lecture 4:
Session 1 (25.03 Thu.)
Mentioned (session 1)
Session 2 (01.04 Thu.)
Mentioned (Session 2)
Session 3 (15.04 Thu.)
Mentioned (Session 3)
Session 4 (22.04 Thu.)
Mentioned (Session 4.1)
Mentioned (Session 4.2)
Session 5 (29.04 Thu.)
Mentioned (Session 5.1)
Mentioned (Session 5.2)
Session 6 (06.05 Thu.)
Mentioned (Session 6.1)
Mentioned (Session 6.2)
Mentioned (Session 9)
D. Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture”, in HPCA 2013 Y. H. Son et al., “Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations,” in ISCA 2013 S. L. Lu et al., “Improving DRAM Latency with Dynamic Asymmetric Subarray,” in MICRO 2015 K. K. Chang et al., “Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM, “ in HPCA 2016
readings.1622740230.txt.gz · Last modified: 2021/06/03 17:10 by hluo