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--- readings [2021/06/03 17:10] – hluo
+++ readings [2021/06/03 17:10] (current) – [Session 6 (06.05 Thu.)] hluo
@@ Line 170: / Line 170: @@
 === Mentioned (Session 9) ===
-{{ tldram_hpca13.pdf | D. Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture”, in  HPCA 2013 }}
+  * {{ tldram_hpca13.pdf | D. Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture”, in  HPCA 2013 }}
-{{ charm_isca13.pdf | Y. H. Son et al., “Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations,” in ISCA 2013 }}
+  * {{ charm_isca13.pdf | Y. H. Son et al., “Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations,” in ISCA 2013 }}
-{{ das_micro15.pdf | S. L. Lu et al., “Improving DRAM Latency with Dynamic Asymmetric Subarray,” in MICRO 2015 }}
+  * {{ das_micro15.pdf | S. L. Lu et al., “Improving DRAM Latency with Dynamic Asymmetric Subarray,” in MICRO 2015 }}
-{{ lisa-dram_hpca16.pdf | K. K. Chang et al., “Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM, “ in HPCA 2016 }}
+  * {{ lisa-dram_hpca16.pdf | K. K. Chang et al., “Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM, “ in HPCA 2016 }}